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4 Commits
toooba-reg
...
800b2d4793
| Author | SHA1 | Date | |
|---|---|---|---|
| 800b2d4793 | |||
| 656cb4d5e8 | |||
| bf7bd16c53 | |||
| c1cf362c70 |
1
.gitignore
vendored
1
.gitignore
vendored
@@ -23,3 +23,4 @@ src_SSITH_P3/Verilog_RTL_sim
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**/TagTableStructure.bsv
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**/GenerateHPMVector.bsv
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**/StatCounters.bsv
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test.txt
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@@ -1,29 +0,0 @@
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# Makefile to create an elf_to_hex executable.
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# The executable creates mem-hex files containing 32-Byte words
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CC = gcc
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# the LIBERARY path needs to be set for Apple devices, e.g.,
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# LIBRARY_PATH="$LIBRARY_PATH:$(brew --prefix)/lib"
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uname_S := $(shell uname -s)
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CFLAGS = -g -o elf_to_hex elf_to_hex.c -lelf
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ifeq ($(uname_S), Darwin)
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CC = clang++
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APPLE_FLAGS = -L /opt/homebrew/lib -I /opt/homebrew/include/libelf -I /opt/homebrew/include
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endif
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elf_to_hex: elf_to_hex.c
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$(CC) $(CFLAGS) $(APPLE_FLAGS)
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# ================================================================
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.PHONY: clean
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clean:
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rm -f *~
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.PHONY: full_clean
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full_clean:
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rm -f *~ elf_to_hex
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@@ -1,12 +0,0 @@
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Copyright (c) 2018 Bluespec, Inc. All Rights Reserved
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This standalone C program takes two command-line arguments, and ELF
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filename and a Mem Hex filename. It reads the ELF file and writes out
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the Mem Hex file.
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It assumes a memory that is:
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- 16 MiB or 256 MiB (see C file)
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- Each word is 32 bytes (256 bits)
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- It starts at byte address 0x_8000_0000
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All of these can be changed by editing the C file.
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@@ -1,382 +0,0 @@
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// Copyright (c) 2013-2018 Bluespec, Inc. All Rights Reserved
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// This program reads an ELF file and outputs a Verilog hex memory
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// image file (suitable for reading using $readmemh).
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// Modifications for CHERI as well as compiling on APPLE devices:
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/*-
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* Copyright (c) 2022 Jonathan Woodruff
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* Copyright (c) 2022 Franz Fuchs
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* All rights reserved.
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*
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* This software was developed by the University of Cambridge
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* Department of Computer Science and Technology under the
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* SIPP (Secure IoT Processor Platform with Remote Attestation)
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* project funded by EPSRC: EP/S030868/1
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*
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* @BERI_LICENSE_HEADER_START@
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*
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* Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
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* license agreements. See the NOTICE file distributed with this work for
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* additional information regarding copyright ownership. BERI licenses this
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* file to you under the BERI Hardware-Software License, Version 1.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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*
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* http://www.beri-open-systems.org/legal/license-1-0.txt
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*
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* Unless required by applicable law or agreed to in writing, Work distributed
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* under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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* CONDITIONS OF ANY KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations under the License.
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*
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* @BERI_LICENSE_HEADER_END@
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*/
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// ================================================================
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// Standard C includes
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <string.h>
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#include <fcntl.h>
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#include <gelf.h>
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#ifdef __APPLE__
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#include <vector>
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#endif
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// ================================================================
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// Memory buffer into which we load the ELF file before
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// writing it back out to the output file.
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// 1 Gigabyte size
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// #define MAX_MEM_SIZE (((uint64_t) 0x400) * ((uint64_t) 0x400) * ((uint64_t) 0x400))
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#define MAX_MEM_SIZE ((uint64_t) 0x90000000)
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#define BASE_ADDR_B 0x80000000lu
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// For 16 MB memory at 0x_8000_0000
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#define MIN_MEM_ADDR_16MB BASE_ADDR_B
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#define MAX_MEM_ADDR_16MB (BASE_ADDR_B + 0x1000000lu)
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// For 1 GB memory at 0x_8000_0000
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#define MIN_MEM_ADDR_1GB BASE_ADDR_B
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#define MAX_MEM_ADDR_1GB (BASE_ADDR_B + 0x40000000lu)
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uint8_t *mem_buf;
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// Features of the ELF binary
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int bitwidth;
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uint64_t min_addr;
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uint64_t max_addr;
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uint64_t pc_start; // Addr of label '_start'
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uint64_t pc_exit; // Addr of label 'exit'
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uint64_t tohost_addr; // Addr of label 'tohost'
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// ================================================================
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// Load an ELF file.
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void c_mem_load_elf (char *elf_filename,
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const char *start_symbol,
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const char *exit_symbol,
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const char *tohost_symbol)
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{
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int fd;
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// int n_initialized = 0;
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Elf *e;
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// Default start, exit and tohost symbols
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if (start_symbol == NULL)
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start_symbol = "_start";
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if (exit_symbol == NULL)
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exit_symbol = "exit";
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if (tohost_symbol == NULL)
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tohost_symbol = "tohost";
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// Verify the elf library version
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if (elf_version (EV_CURRENT) == EV_NONE) {
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fprintf (stderr, "ERROR: c_mem_load_elf: Failed to initialize the libelfg library!\n");
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exit (1);
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}
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// Open the file for reading
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fd = open (elf_filename, O_RDONLY, 0);
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if (fd < 0) {
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fprintf (stderr, "ERROR: c_mem_load_elf: could not open elf input file: %s\n", elf_filename);
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exit (1);
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}
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// Initialize the Elf pointer with the open file
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e = elf_begin (fd, ELF_C_READ, NULL);
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if (e == NULL) {
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fprintf (stderr, "ERROR: c_mem_load_elf: elf_begin() initialization failed!\n");
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exit (1);
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}
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// Verify that the file is an ELF file
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if (elf_kind (e) != ELF_K_ELF) {
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elf_end (e);
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fprintf (stderr, "ERROR: c_mem_load_elf: specified file '%s' is not an ELF file!\n", elf_filename);
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exit (1);
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}
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// Get the ELF header
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GElf_Ehdr ehdr;
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if (gelf_getehdr (e, & ehdr) == NULL) {
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elf_end (e);
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fprintf (stderr, "ERROR: c_mem_load_elf: get_getehdr() failed: %s\n", elf_errmsg(-1));
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exit (1);
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}
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// Is this a 32b or 64 ELF?
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if (gelf_getclass (e) == ELFCLASS32) {
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fprintf (stdout, "c_mem_load_elf: %s is a 32-bit ELF file\n", elf_filename);
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bitwidth = 32;
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}
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else if (gelf_getclass (e) == ELFCLASS64) {
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fprintf (stdout, "c_mem_load_elf: %s is a 64-bit ELF file\n", elf_filename);
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bitwidth = 64;
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}
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else {
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fprintf (stderr, "ERROR: c_mem_load_elf: ELF file '%s' is not 32b or 64b\n", elf_filename);
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elf_end (e);
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exit (1);
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}
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// Verify we are dealing with a RISC-V ELF
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if (ehdr.e_machine != 243) { // EM_RISCV is not defined, but this returns 243 when used with a valid elf file.
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elf_end (e);
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fprintf (stderr, "ERROR: c_mem_load_elf: %s is not a RISC-V ELF file\n", elf_filename);
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exit (1);
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}
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// Verify we are dealing with a little endian ELF
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if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
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elf_end (e);
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fprintf (stderr,
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"ERROR: c_mem_load_elf: %s is a big-endian 64-bit RISC-V executable which is not supported\n",
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elf_filename);
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exit (1);
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}
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// Grab the string section index
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size_t shstrndx;
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shstrndx = ehdr.e_shstrndx;
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// Iterate through each of the sections looking for code that should be loaded
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Elf_Scn *scn = 0;
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GElf_Shdr shdr;
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min_addr = 0xFFFFFFFFFFFFFFFFllu;
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max_addr = 0x0000000000000000llu;
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pc_start = 0xFFFFFFFFFFFFFFFFllu;
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pc_exit = 0xFFFFFFFFFFFFFFFFllu;
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tohost_addr = 0xFFFFFFFFFFFFFFFFllu;
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while ((scn = elf_nextscn (e,scn)) != NULL) {
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// get the header information for this section
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gelf_getshdr (scn, & shdr);
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char *sec_name = elf_strptr (e, shstrndx, shdr.sh_name);
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fprintf (stdout, "Section %-16s: ", sec_name);
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Elf_Data *data = 0;
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// If we find a code/data section, load it into the model
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if ( ((shdr.sh_type == SHT_PROGBITS)
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|| (shdr.sh_type == SHT_NOBITS)
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|| (shdr.sh_type == SHT_INIT_ARRAY)
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|| (shdr.sh_type == SHT_FINI_ARRAY))
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&& ((shdr.sh_flags & SHF_WRITE)
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|| (shdr.sh_flags & SHF_ALLOC)
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|| (shdr.sh_flags & SHF_EXECINSTR))) {
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data = elf_getdata (scn, data);
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// n_initialized += data->d_size;
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if (shdr.sh_addr < min_addr)
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min_addr = shdr.sh_addr;
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if (max_addr < (shdr.sh_addr + data->d_size - 1)) // shdr.sh_size + 4))
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max_addr = shdr.sh_addr + data->d_size - 1; // shdr.sh_size + 4;
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if (max_addr >= MAX_MEM_SIZE) {
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fprintf (stdout, "INTERNAL ERROR: max_addr (0x%0" PRIx64 ") > buffer size (0x%0" PRIx64 ")\n",
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max_addr, MAX_MEM_SIZE);
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fprintf (stdout, " Please increase the #define in this program, recompile, and run again\n");
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fprintf (stdout, " Abandoning this run\n");
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exit (1);
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}
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if (shdr.sh_type != SHT_NOBITS && shdr.sh_addr!=0) {
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memcpy (& (mem_buf [shdr.sh_addr-MIN_MEM_ADDR_1GB]), data->d_buf, data->d_size);
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}
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fprintf (stdout, "addr %16" PRIx64 " to addr %16" PRIx64 "; size 0x%8lx (= %0ld) bytes\n",
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shdr.sh_addr, shdr.sh_addr + data->d_size, data->d_size, data->d_size);
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}
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// If we find the symbol table, search for symbols of interest
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else if (shdr.sh_type == SHT_SYMTAB) {
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fprintf (stdout, "Searching for addresses of '%s', '%s' and '%s' symbols\n",
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start_symbol, exit_symbol, tohost_symbol);
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// Get the section data
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data = elf_getdata (scn, data);
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// Get the number of symbols in this section
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int symbols = shdr.sh_size / shdr.sh_entsize;
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// search for the uart_default symbols we need to potentially modify.
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GElf_Sym sym;
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int i;
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for (i = 0; i < symbols; ++i) {
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// get the symbol data
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gelf_getsym (data, i, &sym);
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// get the name of the symbol
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char *name = elf_strptr (e, shdr.sh_link, sym.st_name);
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// Look for, and remember PC of the start symbol
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if (strcmp (name, start_symbol) == 0) {
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pc_start = sym.st_value;
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}
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// Look for, and remember PC of the exit symbol
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else if (strcmp (name, exit_symbol) == 0) {
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pc_exit = sym.st_value;
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}
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// Look for, and remember addr of 'tohost' symbol
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else if (strcmp (name, tohost_symbol) == 0) {
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tohost_addr = sym.st_value;
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}
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}
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FILE *fp_symbol_table = fopen ("symbol_table.txt", "w");
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if (fp_symbol_table != NULL) {
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fprintf (stdout, "Writing symbols to: symbol_table.txt\n");
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if (pc_start == -1)
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fprintf (stdout, " No '_start' label found\n");
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else
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fprintf (fp_symbol_table, "_start 0x%0" PRIx64 "\n", pc_start);
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if (pc_exit == -1)
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fprintf (stdout, " No 'exit' label found\n");
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else
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fprintf (fp_symbol_table, "exit 0x%0" PRIx64 "\n", pc_exit);
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if (tohost_addr == -1)
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fprintf (stdout, " No 'tohost' symbol found\n");
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else
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fprintf (fp_symbol_table, "tohost 0x%0" PRIx64 "\n", tohost_addr);
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fclose (fp_symbol_table);
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}
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}
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else {
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fprintf (stdout, "Ignored\n");
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}
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}
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elf_end (e);
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fprintf (stdout, "Min addr: %16" PRIx64 " (hex)\n", min_addr);
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fprintf (stdout, "Max addr: %16" PRIx64 " (hex)\n", max_addr);
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}
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// ================================================================
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// Write out from word containing addr1 to word containing addr2
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void write_mem_hex_file (FILE *fp, uint64_t addr1, uint64_t addr2)
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{
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const uint64_t bits_per_raw_mem_word = 256;
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uint64_t bytes_per_raw_mem_word = bits_per_raw_mem_word / 8; // 32
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uint64_t raw_mem_word_align_mask = (~ ((uint64_t) (bytes_per_raw_mem_word - 1)));
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fprintf (stdout, "Subtracting 0x%08" PRIx64 " base from addresses\n", BASE_ADDR_B);
|
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// Align the start and end addrs to raw mem words
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uint64_t a1 = (addr1 & raw_mem_word_align_mask);
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uint64_t a2 = ((addr2 + bytes_per_raw_mem_word - 1) & raw_mem_word_align_mask);
|
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|
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fprintf (fp, "@%07" PRIx64 " // raw_mem addr; byte addr: %08" PRIx64 "\n",
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((a1 - BASE_ADDR_B) / bytes_per_raw_mem_word),
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a1 - BASE_ADDR_B);
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uint64_t addr;
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for (addr = a1; addr < a2; addr += bytes_per_raw_mem_word) {
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for (int j = (bytes_per_raw_mem_word - 1); j >= 0; j--)
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fprintf (fp, "%02x", mem_buf [addr+j-MIN_MEM_ADDR_1GB]);
|
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fprintf (fp, " // raw_mem addr %08" PRIx64 "; byte addr %08" PRIx64 "\n",
|
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((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
|
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(addr - BASE_ADDR_B));
|
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}
|
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|
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// Write last word, if necessary, to avoid warnings about missing locations
|
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if (addr < (MAX_MEM_ADDR_1GB - bytes_per_raw_mem_word)) {
|
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addr = MAX_MEM_ADDR_1GB - bytes_per_raw_mem_word;
|
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fprintf (fp, "@%07" PRIx64 " // last raw_mem addr; byte addr: %08" PRIx64 "\n",
|
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((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
|
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addr - BASE_ADDR_B);
|
||||
for (int j = (bytes_per_raw_mem_word - 1); j >= 0; j--)
|
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fprintf (fp, "%02x", 0);
|
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fprintf (fp, " // raw_mem addr %08" PRIx64 "; byte addr %08" PRIx64 "\n",
|
||||
((addr - BASE_ADDR_B) / bytes_per_raw_mem_word),
|
||||
(addr - BASE_ADDR_B));
|
||||
}
|
||||
}
|
||||
|
||||
// ================================================================
|
||||
|
||||
void print_usage (FILE *fp, int argc, char *argv [])
|
||||
{
|
||||
fprintf (fp, "Usage:\n");
|
||||
fprintf (fp, " %s --help\n", argv [0]);
|
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fprintf (fp, " %s <ELF filename> <mem hex filename>\n", argv [0]);
|
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fprintf (fp, "Reads ELF file and writes a Verilog Hex Memory image file\n");
|
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fprintf (fp, "ELF file should have addresses within this range:\n");
|
||||
fprintf (fp, "< Max: 0x%8" PRIx64 "\n", MAX_MEM_ADDR_1GB);
|
||||
fprintf (fp, ">= Min: 0x%8" PRIx64 "\n", MIN_MEM_ADDR_1GB);
|
||||
}
|
||||
|
||||
// ================================================================
|
||||
|
||||
int main (int argc, char *argv [])
|
||||
{
|
||||
if ((argc == 2) && (strcmp (argv [1], "--help") == 0)) {
|
||||
print_usage (stdout, argc, argv);
|
||||
return 0;
|
||||
}
|
||||
else if (argc != 3) {
|
||||
print_usage (stderr, argc, argv);
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Zero out the memory buffer before loading the ELF file
|
||||
mem_buf = (uint8_t *)(calloc(MAX_MEM_SIZE, sizeof(uint8_t)));
|
||||
if (mem_buf == NULL) {
|
||||
fprintf (stderr, "ERROR: unable to allocate %lxMB for mem_buf\n", MAX_MEM_SIZE / 1024 / 1024);
|
||||
return 1;
|
||||
}
|
||||
|
||||
c_mem_load_elf (argv [1], "_start", "exit", "tohost");
|
||||
|
||||
if ((min_addr < BASE_ADDR_B) || (MAX_MEM_ADDR_1GB <= max_addr)) {
|
||||
print_usage (stderr, argc, argv);
|
||||
exit (1);
|
||||
}
|
||||
|
||||
FILE *fp_out = fopen (argv [2], "w");
|
||||
if (fp_out == NULL) {
|
||||
fprintf (stderr, "ERROR: unable to open file '%s' for output\n", argv [2]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fprintf (stdout, "Writing mem hex to file '%s'\n", argv [2]);
|
||||
write_mem_hex_file (fp_out, BASE_ADDR_B, max_addr);
|
||||
// write_mem_hex_file (fp_out, BASE_ADDR_B, MAX_MEM_ADDR_1GB);
|
||||
|
||||
free(mem_buf);
|
||||
fclose (fp_out);
|
||||
}
|
||||
BIN
Tests/isa/CheriPage
Executable file
BIN
Tests/isa/CheriPage
Executable file
Binary file not shown.
129
Tests/isa/CheriPage.S
Normal file
129
Tests/isa/CheriPage.S
Normal file
@@ -0,0 +1,129 @@
|
||||
.option norvc
|
||||
.option norelax
|
||||
|
||||
# ==================================================
|
||||
# Text section
|
||||
# ==================================================
|
||||
.section .text
|
||||
.globl _start
|
||||
_start:
|
||||
|
||||
vm_boot:
|
||||
# Only hart 0 runs
|
||||
csrr a0, mhartid
|
||||
bnez a0, hang
|
||||
|
||||
# --------------------------------------------------
|
||||
# root_pt[0] -> l1_pt
|
||||
# --------------------------------------------------
|
||||
cllc c0, l1_pt
|
||||
li t2, 4096
|
||||
csetbounds c0, c0, t2
|
||||
|
||||
cgetaddr t0, c0
|
||||
srli t0, t0, 12
|
||||
slli t0, t0, 10
|
||||
ori t0, t0, 0x1 # V bit
|
||||
|
||||
cllc c1, root_pt
|
||||
li t2, 4096
|
||||
csetbounds c1, c1, t2
|
||||
sd t0, 0(c1)
|
||||
|
||||
# --------------------------------------------------
|
||||
# l1_pt[0] -> l0_pt
|
||||
# --------------------------------------------------
|
||||
cllc c0, l0_pt
|
||||
li t2, 4096
|
||||
csetbounds c0, c0, t2
|
||||
|
||||
cgetaddr t0, c0
|
||||
srli t0, t0, 12
|
||||
slli t0, t0, 10
|
||||
ori t0, t0, 0x1 # V bit
|
||||
|
||||
cllc c1, l1_pt
|
||||
li t2, 4096
|
||||
csetbounds c1, c1, t2
|
||||
sd t0, 0(c1)
|
||||
|
||||
# --------------------------------------------------
|
||||
# l0_pt[0] -> leaf (RWX)
|
||||
# --------------------------------------------------
|
||||
li t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6) # V R W X A
|
||||
|
||||
cllc c1, l0_pt
|
||||
li t2, 4096
|
||||
csetbounds c1, c1, t2
|
||||
sd t0, 0(c1)
|
||||
|
||||
# --------------------------------------------------
|
||||
# Enable Sv39 paging
|
||||
# --------------------------------------------------
|
||||
cllc c0, root_pt
|
||||
li t2, 4096
|
||||
csetbounds c0, c0, t2
|
||||
|
||||
cgetaddr t0, c0
|
||||
srli t0, t0, 12
|
||||
li t1, (8 << 60) # MODE = Sv39
|
||||
or t0, t0, t1
|
||||
csrw satp, t0
|
||||
sfence.vma zero, zero
|
||||
|
||||
# --------------------------------------------------
|
||||
# Safe data access
|
||||
# --------------------------------------------------
|
||||
cllc c2, test_buf
|
||||
li t2, 16
|
||||
csetbounds c2, c2, t2
|
||||
|
||||
li t3, 0x1122334455667788
|
||||
sd t3, 0(c2)
|
||||
ld t4, 0(c2)
|
||||
bne t3, t4, hang
|
||||
|
||||
# --------------------------------------------------
|
||||
# Signal success
|
||||
# --------------------------------------------------
|
||||
cllc c0, tohost
|
||||
li t2, 8
|
||||
csetbounds c0, c0, t2
|
||||
li t1, 1
|
||||
sd t1, 0(c0)
|
||||
|
||||
hang:
|
||||
wfi
|
||||
j hang
|
||||
|
||||
# ==================================================
|
||||
# Data section (aligned, contiguous, no .org)
|
||||
# ==================================================
|
||||
.section .data
|
||||
.align 12
|
||||
.globl root_pt
|
||||
root_pt:
|
||||
.zero 4096 # Root page table
|
||||
|
||||
.align 12
|
||||
.globl l1_pt
|
||||
l1_pt:
|
||||
.zero 4096 # Level 1 page table
|
||||
|
||||
.align 12
|
||||
.globl l0_pt
|
||||
l0_pt:
|
||||
.zero 4096 # Level 0 page table
|
||||
|
||||
.align 3
|
||||
.globl test_buf
|
||||
test_buf:
|
||||
.zero 16 # Test buffer
|
||||
|
||||
.globl tohost
|
||||
tohost:
|
||||
.dword 0
|
||||
|
||||
.globl fromhost
|
||||
fromhost:
|
||||
.dword 0
|
||||
230
Tests/isa/PageRead.S
Normal file
230
Tests/isa/PageRead.S
Normal file
@@ -0,0 +1,230 @@
|
||||
.option norvc
|
||||
.option norelax
|
||||
|
||||
# ==================================================
|
||||
# Text section
|
||||
# ==================================================
|
||||
.section .text
|
||||
.globl _start
|
||||
.globl vm_boot
|
||||
|
||||
_start:
|
||||
vm_boot:
|
||||
# --------------------------------------------------
|
||||
# Only hart 0 runs
|
||||
# --------------------------------------------------
|
||||
csrr a0, mhartid
|
||||
bnez a0, hang
|
||||
|
||||
# --------------------------------------------------
|
||||
# Build page tables
|
||||
# --------------------------------------------------
|
||||
|
||||
#
|
||||
# Page table setup (Sv39) — binary + hex example
|
||||
#
|
||||
# Purpose:
|
||||
# Build a VALID page table entry (PTE) in the root page table
|
||||
# that points to the next-level page table (l1_pt).
|
||||
#
|
||||
# Assume:
|
||||
# l1_pt physical address =
|
||||
# binary: 00000000 10000000 01000000 00110000 00000000
|
||||
# hex: 0x0000000080403000
|
||||
# (page aligned, lower 12 bits = 0)
|
||||
#
|
||||
# Step-by-step instruction meaning:
|
||||
#
|
||||
# la t0, l1_pt
|
||||
# Load physical address of l1_pt.
|
||||
#
|
||||
# t0 =
|
||||
# binary: 00000000 10000000 01000000 00110000 00000000
|
||||
# hex: 0x0000000080403000
|
||||
#
|
||||
# srli t0, t0, 12
|
||||
# Drop 12-bit page offset → extract Physical Page Number (PPN).
|
||||
#
|
||||
# t0 (PPN) =
|
||||
# binary: 00000000 00000000 10000000 01000000 0011
|
||||
# hex: 0x0000000000080403
|
||||
#
|
||||
# slli t0, t0, 10
|
||||
# Shift PPN into PTE bit positions [63:10].
|
||||
# Bits [9:0] are flags.
|
||||
#
|
||||
# t0 =
|
||||
# binary: 00000000 00000000 10000000 01000000 0011 0000000000
|
||||
# hex: 0x0000000020100C00
|
||||
#
|
||||
# ori t0, t0, 1
|
||||
# Set bit 0 (V = Valid).
|
||||
#
|
||||
# t0 (final PTE) =
|
||||
# binary: 00000000 00000000 10000000 01000000 0011 0000000001
|
||||
# hex: 0x0000000020100C01
|
||||
#
|
||||
# Memory effect:
|
||||
#
|
||||
# root_pt[0] =
|
||||
# bit index:
|
||||
# 63 10 9 0
|
||||
# +----------------------------------+----------+
|
||||
# | PPN = 0x0000000000080403 | V = 1 |
|
||||
# +----------------------------------+----------+
|
||||
#
|
||||
# binary: 00000000 00000000 10000000 01000000 0011 0000000001
|
||||
# hex: 0x0000000020100C01
|
||||
#
|
||||
# Result:
|
||||
# Root page table entry 0 is VALID and points to l1_pt.
|
||||
# The MMU uses this entry to continue the Sv39 page-table walk.
|
||||
#
|
||||
|
||||
|
||||
# root_pt[0] -> l1_pt
|
||||
la t0, l1_pt
|
||||
srli t0, t0, 12 # PPN
|
||||
slli t0, t0, 10 # PTE format
|
||||
ori t0, t0, 0x1 # V
|
||||
la t1, root_pt
|
||||
sd t0, 0(t1)
|
||||
|
||||
# l1_pt[0] -> l0_pt
|
||||
la t0, l0_pt
|
||||
srli t0, t0, 12
|
||||
slli t0, t0, 10
|
||||
ori t0, t0, 0x1 # V
|
||||
la t1, l1_pt
|
||||
sd t0, 0(t1)
|
||||
|
||||
# l0_pt[0] -> identity mapping (RWX)
|
||||
li t0, (1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<6) # V R W X A
|
||||
la t1, l0_pt
|
||||
sd t0, 0(t1)
|
||||
|
||||
# --------------------------------------------------
|
||||
# Enable Sv39 paging
|
||||
# --------------------------------------------------
|
||||
|
||||
# Enable virtual memory (Sv39) — SATP setup diagram (binary)
|
||||
#
|
||||
# Assume:
|
||||
# root_pt physical address =
|
||||
# 00000000 10000000 01000000 00010000 00000000
|
||||
# (4 KB aligned, lower 12 bits = 0)
|
||||
#
|
||||
# Instruction flow:
|
||||
#
|
||||
# la t0, root_pt
|
||||
# t0 =
|
||||
# 00000000 10000000 01000000 00010000 00000000
|
||||
#
|
||||
# srli t0, t0, 12 ; extract PPN
|
||||
# t0 (PPN) =
|
||||
# 00000000 00000000 10000000 01000000 0001
|
||||
#
|
||||
# li t1, (8 << 60) ; MODE = Sv39
|
||||
# t1 =
|
||||
# 1000 0000000000000000000000000000000000000000000000000000
|
||||
# ^^^^
|
||||
# MODE[63:60] = 1000 (Sv39)
|
||||
#
|
||||
# or t0, t0, t1
|
||||
# satp value =
|
||||
# 1000 0000000000000000000000000000000010000000010000000001
|
||||
# |<-- MODE -->|<----------- ASID ---------->|<---- PPN ---->|
|
||||
#
|
||||
# csrw satp, t0
|
||||
# satp register loaded:
|
||||
#
|
||||
# 63 60 59 44 43 0
|
||||
# +------+----------------------------------+----------------+
|
||||
# |1000 |0000000000000000 |0000000010000000010000000001|
|
||||
# +------+----------------------------------+----------------+
|
||||
# MODE=Sv39 ASID=0 root_pt PPN
|
||||
#
|
||||
# sfence.vma zero, zero
|
||||
# Flush all TLB entries so new page tables are used
|
||||
#
|
||||
# Meaning:
|
||||
# - Virtual memory enabled in Sv39 mode
|
||||
# - Root page table base = root_pt
|
||||
# - ASID = 0
|
||||
# - MMU now performs 3-level page table walks
|
||||
#
|
||||
|
||||
la t0, root_pt
|
||||
srli t0, t0, 12
|
||||
li t1, (8 << 60) # MODE=Sv39
|
||||
or t0, t0, t1
|
||||
csrw satp, t0
|
||||
sfence.vma zero, zero
|
||||
|
||||
# --------------------------------------------------
|
||||
# Write data to memory (safe area)
|
||||
# --------------------------------------------------
|
||||
la t2, test_buf
|
||||
li t3, 0x1122334455667788
|
||||
sd t3, 0(t2)
|
||||
|
||||
# --------------------------------------------------
|
||||
# Read data back
|
||||
# --------------------------------------------------
|
||||
ld t4, 0(t2)
|
||||
|
||||
# Optional check (simple)
|
||||
bne t3, t4, hang
|
||||
|
||||
# --------------------------------------------------
|
||||
# Signal success
|
||||
# --------------------------------------------------
|
||||
la t0, tohost
|
||||
li t1, 1
|
||||
sd t1, 0(t0)
|
||||
|
||||
hang:
|
||||
wfi
|
||||
j hang
|
||||
|
||||
# ==================================================
|
||||
# Required test symbol
|
||||
# ==================================================
|
||||
.globl exit
|
||||
exit:
|
||||
j exit
|
||||
|
||||
# ==================================================
|
||||
# Data section
|
||||
# ==================================================
|
||||
.section .data
|
||||
.align 3
|
||||
|
||||
.globl tohost
|
||||
.globl fromhost
|
||||
tohost:
|
||||
.dword 0
|
||||
fromhost:
|
||||
.dword 0
|
||||
|
||||
# --------------------------------------------------
|
||||
# Test buffer (safe data memory)
|
||||
# --------------------------------------------------
|
||||
.align 3
|
||||
test_buf:
|
||||
.zero 16
|
||||
|
||||
# --------------------------------------------------
|
||||
# Page tables (must be 4 KiB each)
|
||||
# --------------------------------------------------
|
||||
.align 12
|
||||
root_pt:
|
||||
.zero 4096
|
||||
|
||||
.align 12
|
||||
l1_pt:
|
||||
.zero 4096
|
||||
|
||||
.align 12
|
||||
l0_pt:
|
||||
.zero 4096
|
||||
BIN
Tests/isa/PageReadWrite
Executable file
BIN
Tests/isa/PageReadWrite
Executable file
Binary file not shown.
@@ -12,7 +12,7 @@ _start:
|
||||
vm_boot:
|
||||
# Only hart 0
|
||||
csrr a0, mhartid
|
||||
bnez a0, hang
|
||||
bnez a0, hang.
|
||||
|
||||
# --------------------------------------------------
|
||||
# Build page table entries
|
||||
|
||||
@@ -1,43 +0,0 @@
|
||||
make -C ../../Tests/elf_to_hex
|
||||
make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
|
||||
make[1]: 'elf_to_hex' is up to date.
|
||||
make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
|
||||
../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/rv64ui-p-add Mem.hex
|
||||
c_mem_load_elf: ../../Tests/isa/rv64ui-p-add is a 64-bit ELF file
|
||||
Section .text.init : addr 80000000 to addr 80000644; size 0x 644 (= 1604) bytes
|
||||
Section .tohost : addr 80001000 to addr 80001048; size 0x 48 (= 72) bytes
|
||||
Section .riscv.attributes: Ignored
|
||||
Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols
|
||||
Writing symbols to: symbol_table.txt
|
||||
No 'exit' label found
|
||||
Section .strtab : Ignored
|
||||
Section .shstrtab : Ignored
|
||||
Min addr: 80000000 (hex)
|
||||
Max addr: 80001047 (hex)
|
||||
Writing mem hex to file 'Mem.hex'
|
||||
Subtracting 0x80000000 base from addresses
|
||||
./exe_HW_sim +v1 +tohost
|
||||
================================================================
|
||||
Bluespec RISC-V standalone system simulation v1.2
|
||||
Copyright (c) 2017-2018 Bluespec, Inc. All Rights Reserved.
|
||||
================================================================
|
||||
2: top.dut_soc_top.rl_reset_start_initial ...
|
||||
---- allocated socket for RVFI_DII
|
||||
---- RVFI_DII_PORT environment variable not defined, using default port 5001 instead
|
||||
---- RVFI_DII socket listening on port 5001
|
||||
req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
|
||||
req addr: 'h0000000000000000, zeroed_0_start: 'h0000000000000000-'h0000000000040000, zeroed_1_start: 'h0000000001f80000-'h0000000001fffff8
|
||||
74: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
|
||||
SoC address map:
|
||||
Boot ROM: 0x1000 .. 0x2000
|
||||
Mem0 Controller: 0x80000000 .. 0xc0000000
|
||||
UART0: 0xc0000000 .. 0xc0000080
|
||||
74: top.dut_soc_top.rl_reset_complete_initial
|
||||
INFO: watch_tohost 1, tohost_addr = 0x80001000, fromhost_addr = 0x0
|
||||
75: top.dut_soc_top.method start (tohost 80001000, fromhost 0)
|
||||
101: top.dut_soc_top.rl_step_0, n = 0, do_release
|
||||
101: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 0)
|
||||
101: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 0, fromhostAddr 0
|
||||
102: top.dut_soc_top.rl_ctrl_req
|
||||
102: top.dut_soc_top.proc.method start: startpc 80000000, tohostAddr 80001000, fromhostAddr 0
|
||||
102: top.dut_soc_top do_release(restartRunning: True, to_host_addr: 80001000)
|
||||
@@ -1,134 +0,0 @@
|
||||
@0000000 // raw_mem addr; byte addr: 00000000
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000000; byte addr 00000000
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000001; byte addr 00000020
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000002; byte addr 00000040
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000003; byte addr 00000060
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000004; byte addr 00000080
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000005; byte addr 000000a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000006; byte addr 000000c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000007; byte addr 000000e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000008; byte addr 00000100
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000009; byte addr 00000120
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000a; byte addr 00000140
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000b; byte addr 00000160
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000c; byte addr 00000180
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000d; byte addr 000001a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000e; byte addr 000001c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000000f; byte addr 000001e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000010; byte addr 00000200
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000011; byte addr 00000220
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000012; byte addr 00000240
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000013; byte addr 00000260
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000014; byte addr 00000280
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000015; byte addr 000002a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000016; byte addr 000002c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000017; byte addr 000002e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000018; byte addr 00000300
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000019; byte addr 00000320
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001a; byte addr 00000340
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001b; byte addr 00000360
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001c; byte addr 00000380
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001d; byte addr 000003a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001e; byte addr 000003c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000001f; byte addr 000003e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000020; byte addr 00000400
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000021; byte addr 00000420
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000022; byte addr 00000440
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000023; byte addr 00000460
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000024; byte addr 00000480
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000025; byte addr 000004a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000026; byte addr 000004c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000027; byte addr 000004e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000028; byte addr 00000500
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000029; byte addr 00000520
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002a; byte addr 00000540
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002b; byte addr 00000560
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002c; byte addr 00000580
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002d; byte addr 000005a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002e; byte addr 000005c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000002f; byte addr 000005e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000030; byte addr 00000600
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000031; byte addr 00000620
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000032; byte addr 00000640
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000033; byte addr 00000660
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000034; byte addr 00000680
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000035; byte addr 000006a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000036; byte addr 000006c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000037; byte addr 000006e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000038; byte addr 00000700
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000039; byte addr 00000720
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003a; byte addr 00000740
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003b; byte addr 00000760
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003c; byte addr 00000780
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003d; byte addr 000007a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003e; byte addr 000007c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000003f; byte addr 000007e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000040; byte addr 00000800
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000041; byte addr 00000820
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000042; byte addr 00000840
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000043; byte addr 00000860
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000044; byte addr 00000880
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000045; byte addr 000008a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000046; byte addr 000008c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000047; byte addr 000008e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000048; byte addr 00000900
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000049; byte addr 00000920
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004a; byte addr 00000940
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004b; byte addr 00000960
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004c; byte addr 00000980
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004d; byte addr 000009a0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004e; byte addr 000009c0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000004f; byte addr 000009e0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000050; byte addr 00000a00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000051; byte addr 00000a20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000052; byte addr 00000a40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000053; byte addr 00000a60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000054; byte addr 00000a80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000055; byte addr 00000aa0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000056; byte addr 00000ac0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000057; byte addr 00000ae0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000058; byte addr 00000b00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000059; byte addr 00000b20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005a; byte addr 00000b40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005b; byte addr 00000b60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005c; byte addr 00000b80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005d; byte addr 00000ba0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005e; byte addr 00000bc0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000005f; byte addr 00000be0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000060; byte addr 00000c00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000061; byte addr 00000c20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000062; byte addr 00000c40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000063; byte addr 00000c60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000064; byte addr 00000c80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000065; byte addr 00000ca0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000066; byte addr 00000cc0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000067; byte addr 00000ce0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000068; byte addr 00000d00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000069; byte addr 00000d20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006a; byte addr 00000d40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006b; byte addr 00000d60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006c; byte addr 00000d80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006d; byte addr 00000da0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006e; byte addr 00000dc0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000006f; byte addr 00000de0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000070; byte addr 00000e00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000071; byte addr 00000e20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000072; byte addr 00000e40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000073; byte addr 00000e60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000074; byte addr 00000e80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000075; byte addr 00000ea0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000076; byte addr 00000ec0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000077; byte addr 00000ee0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000078; byte addr 00000f00
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000079; byte addr 00000f20
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007a; byte addr 00000f40
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007b; byte addr 00000f60
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007c; byte addr 00000f80
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007d; byte addr 00000fa0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007e; byte addr 00000fc0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 0000007f; byte addr 00000fe0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000080; byte addr 00001000
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000081; byte addr 00001020
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 00000082; byte addr 00001040
|
||||
@07fffff // last raw_mem addr; byte addr: 0fffffe0
|
||||
0000000000000000000000000000000000000000000000000000000000000000 // raw_mem addr 007fffff; byte addr 0fffffe0
|
||||
@@ -10,7 +10,9 @@ BSC_COMPILATION_FLAGS += -verbose
|
||||
|
||||
# TEST ?= rv64ui-p-add
|
||||
# TEST ?= rv64um-v-mulw
|
||||
TEST ?= Page
|
||||
# TEST ?= Page
|
||||
TEST ?= PageReadWrite
|
||||
# TEST ?= CheriPage
|
||||
|
||||
#================================================================
|
||||
# Parameter settings for MIT RISCY, setup paths etc. for Include_Common
|
||||
|
||||
@@ -1,218 +0,0 @@
|
||||
make -C ../../Tests/elf_to_hex
|
||||
make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
|
||||
make[1]: 'elf_to_hex' is up to date.
|
||||
make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex'
|
||||
../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/Page Mem.hex
|
||||
c_mem_load_elf: ../../Tests/isa/Page is a 64-bit ELF file
|
||||
Section .text : addr 80000000 to addr 80000094; size 0x 94 (= 148) bytes
|
||||
Section .data : addr 80002000 to addr 80006000; size 0x 4000 (= 16384) bytes
|
||||
Section .riscv.attributes: Ignored
|
||||
Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols
|
||||
Writing symbols to: symbol_table.txt
|
||||
Section .strtab : Ignored
|
||||
Section .shstrtab : Ignored
|
||||
Min addr: 80000000 (hex)
|
||||
Max addr: 80005fff (hex)
|
||||
Writing mem hex to file 'Mem.hex'
|
||||
Subtracting 0x80000000 base from addresses
|
||||
./exe_HW_sim +v1 +tohost
|
||||
Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 768 to 33554430.
|
||||
1: top.soc_top.rl_reset_start_initial ...
|
||||
11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
|
||||
SoC address map:
|
||||
Boot ROM: 0x1000 .. 0x2000
|
||||
Mem0 Controller: 0x80000000 .. 0xc0000000
|
||||
UART0: 0xc0000000 .. 0xc0000080
|
||||
11: top.soc_top.rl_reset_complete_initial
|
||||
================================================================
|
||||
Bluespec RISC-V standalone system simulation v1.2
|
||||
Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
|
||||
================================================================
|
||||
INFO: watch_tohost 1, tohost_addr = 0x80002000, fromhost_addr = 0x0
|
||||
12: top.soc_top.method start (tohost 80002000, fromhost 0)
|
||||
100: top.soc_top.rl_step_0, n = 0, do_release
|
||||
100: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
|
||||
100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
|
||||
101: top.soc_top.rl_ctrl_req
|
||||
101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 80002000, fromhostAddr 0
|
||||
101: top.soc_top do_release(restartRunning: True, to_host_addr: 80002000)
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 1: r 40 <= 0000000000000400000000001fffff44000000
|
||||
[RFile] wr_ 0: r 41 <= 0000000000000408000000001fffff44000000
|
||||
instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167
|
||||
instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 42 <= 0000000000000000000000001fffff44000000
|
||||
instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
3360 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V False False False False False False False False True True True True True True True True > }, spec_bits: 'h000 }
|
||||
3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
|
||||
[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, loadTags: False }
|
||||
[RFile] wr_ 3: r 43 <= 0000000020000000000000001fffff44000000
|
||||
[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000 > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000 > }
|
||||
instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403
|
||||
[ALU redirect - 1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
|
||||
[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02 > ; <V 'h02 'h02 > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False > > ; 'h1 ; <V 'h03 'h02 > ; <V 'h00 'h00 >
|
||||
instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 45 <= 0000000000000000000000001fffff44000000
|
||||
instret:5 PC:0x1ffff0000000000000000000080000000 instr:0xf1402573 iType:Csr [doCommitSystemInst] 1155
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Br, execFunc: tagged Br Neq, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0a, rn2 'h00, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000084 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'h000, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h002 }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h45, src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffff8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 47 <= 0000000020001002000000001fffff44000000
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00005000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[RFile] wr_ 1: r 48 <= 0000000020001000000000001fffff44000000
|
||||
instret:6 PC:0x1ffff0000000000000000000080000004 instr:0x08051263 iType:Br [doCommitNormalInst [0]] 1167
|
||||
instret:7 PC:0x1ffff0000000000000000000080000008 instr:0x00004297 iType:Auipc [doCommitNormalInst [1]] 1167
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h18}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffd8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 49 <= 0000000000020001000000001fffff44000000
|
||||
instret:8 PC:0x1ffff000000000000000000008000000c instr:0xff828293 iType:Alu [doCommitNormalInst [0]] 1168
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h52, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h51, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h52, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 1: r 4a <= 0000000008000400000000001fffff44000000
|
||||
11690 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
instret:9 PC:0x1ffff0000000000000000000080000010 instr:0x00c2d293 iType:Alu [doCommitNormalInst [0]] 1169
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00004000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 4b <= 0000000008000400400000001fffff44000000
|
||||
[RFile] wr_ 1: r 4c <= 0000000020000c07000000001fffff44000000
|
||||
11700 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4b, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:10 PC:0x1ffff0000000000000000000080000014 instr:0x00a29293 iType:Alu [doCommitNormalInst [0]] 1170
|
||||
[RFile] wr_ 0: r 4d <= 0000000020000c00000000001fffff44000000
|
||||
[RFile] wr_ 1: r 4f <= 000000002000140a000000001fffff44000000
|
||||
11710 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000020001001 o: 'h0000000020001001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
instret:11 PC:0x1ffff0000000000000000000080000018 instr:0x0012e293 iType:Alu [doCommitNormalInst [0]] 1171
|
||||
instret:12 PC:0x1ffff000000000000000000008000001c instr:0x00003317 iType:Auipc [doCommitNormalInst [1]] 1171
|
||||
[RFile] wr_ 1: r 50 <= 0000000020001400000000001fffff44000000
|
||||
11720 : [doFinishMem] DTlbResp { resp: <'h0000000080003000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080003000 o: 'h0000000080003000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080003000, check_high: 'h00000000080003008, check_inclusive: True } }, specBits: 'h000 }
|
||||
instret:13 PC:0x1ffff0000000000000000000080000020 instr:0xfe430313 iType:Alu [doCommitNormalInst [0]] 1172
|
||||
[RFile] wr_ 0: r 51 <= 0000000000020001400000001fffff44000000
|
||||
[RFile] wr_ 1: r 54 <= 000000002000100f000000001fffff44000000
|
||||
instret:14 PC:0x1ffff0000000000000000000080000024 instr:0x00533023 iType:St [doCommitNormalInst [0]] 1173
|
||||
instret:15 PC:0x1ffff0000000000000000000080000028 instr:0x00005297 iType:Auipc [doCommitNormalInst [1]] 1173
|
||||
[RFile] wr_ 1: r 52 <= 0000000008000500000000001fffff44000000
|
||||
[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080003000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000020001001 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 }
|
||||
11740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
|
||||
instret:16 PC:0x1ffff000000000000000000008000002c instr:0xfd828293 iType:Alu [doCommitNormalInst [0]] 1174
|
||||
instret:17 PC:0x1ffff0000000000000000000080000030 instr:0x00c2d293 iType:Alu [doCommitNormalInst [1]] 1174
|
||||
[RFile] wr_ 0: r 53 <= 0000000008000500400000001fffff44000000
|
||||
11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
|
||||
11750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
instret:18 PC:0x1ffff0000000000000000000080000034 instr:0x00a29293 iType:Alu [doCommitNormalInst [0]] 1175
|
||||
instret:19 PC:0x1ffff0000000000000000000080000038 instr:0x0012e293 iType:Alu [doCommitNormalInst [0]] 1176
|
||||
instret:20 PC:0x1ffff000000000000000000008000003c instr:0x00004317 iType:Auipc [doCommitNormalInst [1]] 1176
|
||||
11770 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080003000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h04}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00005000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h58, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000005f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
12230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffb4 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h58, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
12240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffa8 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00003000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 1: r 55 <= 0000000020001000000000001fffff44000000
|
||||
12250 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000020001401 o: 'h0000000020001401 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
12250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffff }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Srl, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 58 <= 0000000020001413000000001fffff44000000
|
||||
[RFile] wr_ 1: r 57 <= 0000000000000017c00000001fffff44000000
|
||||
12260 : [doFinishMem] DTlbResp { resp: <'h0000000080004000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080004000 o: 'h0000000080004000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080004000, check_high: 'h00000000080004008, check_inclusive: True } }, specBits: 'h000 }
|
||||
12260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
instret:21 PC:0x1ffff0000000000000000000080000040 instr:0xfc430313 iType:Alu [doCommitNormalInst [0]] 1226
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Or, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5d, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h06, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000003f }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 59 <= 0000000020001400000000001fffff44000000
|
||||
12270 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000000000005f o: 'h000000000000005f b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h06, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
instret:22 PC:0x1ffff0000000000000000000080000044 instr:0x00533023 iType:St [doCommitNormalInst [0]] 1227
|
||||
instret:23 PC:0x1ffff0000000000000000000080000048 instr:0x05f00293 iType:Alu [doCommitNormalInst [1]] 1227
|
||||
[RFile] wr_ 1: r 5b <= 0000000020000c16000000001fffff44000000
|
||||
12280 : [doFinishMem] DTlbResp { resp: <'h0000000080005000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080005000 o: 'h0000000080005000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080005000, check_high: 'h00000000080005008, check_inclusive: True } }, specBits: 'h000 }
|
||||
instret:24 PC:0x1ffff000000000000000000008000004c instr:0x00005317 iType:Auipc [doCommitNormalInst [0]] 1228
|
||||
instret:25 PC:0x1ffff0000000000000000000080000050 instr:0xfb430313 iType:Alu [doCommitNormalInst [1]] 1228
|
||||
[RFile] wr_ 0: r 5c <= 0000000020000c00000000001fffff44000000
|
||||
instret:26 PC:0x1ffff0000000000000000000080000054 instr:0x00533023 iType:St [doCommitNormalInst [0]] 1229
|
||||
instret:27 PC:0x1ffff0000000000000000000080000058 instr:0x00003297 iType:Auipc [doCommitNormalInst [1]] 1229
|
||||
[RFile] wr_ 0: r 5e <= 3fffffffffffffffcfff00001fffff44000000
|
||||
[RFile] wr_ 1: r 5d <= 0000000000020000c00000001fffff44000000
|
||||
instret:28 PC:0x1ffff000000000000000000008000005c instr:0xfa828293 iType:Alu [doCommitNormalInst [0]] 1230
|
||||
[RFile] wr_ 1: r 5f <= 2000000000000000080000001fffff44000000
|
||||
instret:29 PC:0x1ffff0000000000000000000080000060 instr:0x00c2d293 iType:Alu [doCommitNormalInst [0]] 1231
|
||||
instret:30 PC:0x1ffff0000000000000000000080000064 instr:0xfff0031b iType:Alu [doCommitNormalInst [1]] 1231
|
||||
[RFile] wr_ 0: r 60 <= 2000000000020000c80000001fffff44000000
|
||||
instret:31 PC:0x1ffff0000000000000000000080000068 instr:0x03f31313 iType:Alu [doCommitNormalInst [0]] 1232
|
||||
instret:32 PC:0x1ffff000000000000000000008000006c instr:0x0062e2b3 iType:Alu [doCommitNormalInst [0]] 1233
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Valid csrAddrSATP, scr: tagged Invalid , imm: tagged Invalid }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
12490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080003000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
|
||||
12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080003000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8024 }
|
||||
[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000020001001 'h0000000000000000 > } }
|
||||
12500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000020001001 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
|
||||
[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080004000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000020001401 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8044 }
|
||||
12510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
12520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
12540 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080004000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
|
||||
13110 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080004000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h0 }
|
||||
13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8044 }
|
||||
[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h0000000020001401 'h0000000000000000 > } }
|
||||
13120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h0000000020001401 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
|
||||
[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080005000, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h000000000000005f 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8054 }
|
||||
13130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
|
||||
13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: <V False True False True >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
|
||||
13140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
|
||||
13160 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080005000, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False }
|
||||
13640 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080005000, toState: M, child: , data: tagged Valid CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > }, id: 'h1 }
|
||||
13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: <V False False False False >, data: <V <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } }, repInfo: , setAuxData: tagged Invalid }
|
||||
13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs:
|
||||
13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 }
|
||||
[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V True True True True True True True True False False False False False False False False >, shiftedData: TaggedData { tag: False, data: <V 'h000000000000005f 'h0000000000000000 > } }
|
||||
13650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False >, data: <V <V 'h000000000000005f 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > <V 'h0000000000000000 'h0000000000000000 > > } ; tagged Invalid
|
||||
instret:33 PC:0x1ffff0000000000000000000080000070 instr:0x18029073 iType:Csr [doCommitSystemInst] 1366
|
||||
instret:34 PC:0x1ffff0000000000000000000080000074 instr:0x12000073 iType:SFence [doCommitSystemInst] 1637
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h08}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffff88 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h63, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00002000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
19100 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 1: r 63 <= 000000002000081e000000001fffff44000000
|
||||
19110 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[RFile] wr_ 0: r 64 <= 0000000020000800000000001fffff44000000
|
||||
[RFile] wr_ 1: r 65 <= 0000000000000000400000001fffff44000000
|
||||
19120 : [doExeMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, shiftBEData: <V True True True True True True True True False False False False False False False False > }, spec_bits: 'h000 }
|
||||
instret:35 PC:0x1ffff0000000000000000000080000078 instr:0x00002297 iType:Auipc [doCommitNormalInst [0]] 1912
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
19130 : [doFinishMem] DTlbResp { resp: <'h0000000080002000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False >, vaddr: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080002000, check_high: 'h00000000080002008, check_inclusive: True } }, specBits: 'h000 }
|
||||
instret:36 PC:0x1ffff000000000000000000008000007c instr:0xf8828293 iType:Alu [doCommitNormalInst [0]] 1913
|
||||
instret:37 PC:0x1ffff0000000000000000000080000080 instr:0x00100313 iType:Alu [doCommitNormalInst [1]] 1913
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080002000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8084 }; MMIOCRq { addr: 'h0000000080002000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000 > }, loadTags: False }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
[mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
|
||||
1919: mmioPlatform.rl_tohost: 0x1 (= 1)
|
||||
PASS
|
||||
@@ -320,6 +320,7 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
|
||||
// pipeline fifos
|
||||
let dispToRegQ <- mkMemDispToRegFifo;
|
||||
let regToExeQ <- mkMemRegToExeFifo;
|
||||
// let trollToExeQ <- mkMemRegToExeFifo;
|
||||
|
||||
// wire to recv bypass
|
||||
Vector#(TMul#(2, AluExeNum), RWire#(Tuple2#(PhyRIndx, CapPipe))) bypassWire <- replicateM(mkRWire);
|
||||
@@ -530,7 +531,14 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
|
||||
if(x.regs.src1 matches tagged Valid .src1 &&& src1 != 0) begin
|
||||
rVal1 <- readRFBypass(src1, regsReady.src1, inIfc.rf_rd1(src1), bypassWire);
|
||||
end
|
||||
if (x.ddc_offset) rVal1 = setAddr(ddc, getAddr(rVal1)).value;
|
||||
if (x.ddc_offset) begin
|
||||
$display("calling set address");
|
||||
rVal1 = setAddr(ddc, getAddr(rVal1)).value;
|
||||
end
|
||||
else begin
|
||||
$display("no called set address");
|
||||
end
|
||||
$display("outside if and else");
|
||||
|
||||
// get rVal2 (check bypass)
|
||||
CapPipe rVal2 = nullCap;
|
||||
@@ -597,9 +605,12 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
|
||||
endrule
|
||||
|
||||
rule doExeMem;
|
||||
$display("do exe");
|
||||
regToExeQ.deq;
|
||||
let regToExe = regToExeQ.first;
|
||||
let x = regToExe.data;
|
||||
// trollToExeQ.enq(regToExe);
|
||||
// ==============================
|
||||
if(verbose) $display("%t : [doExeMem] ", $time, fshow(regToExe));
|
||||
|
||||
let shiftBE = DataMemAccess(x.shiftBEData);
|
||||
@@ -647,10 +658,19 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
|
||||
endrule
|
||||
|
||||
rule doFinishMem;
|
||||
$display("do finish mem");
|
||||
// trollToExeQ.deq;
|
||||
// let regToExe = trollToExeQ.first;
|
||||
// let lol = regToExe.data;
|
||||
// =============================
|
||||
dTlb.deqProcResp;
|
||||
let dTlbResp = dTlb.procResp;
|
||||
let x = dTlbResp.inst;
|
||||
let x = dTlbResp.inst;
|
||||
let {paddr, expCause, allowCapPTE} = dTlbResp.resp;
|
||||
// paddr = getAddr(lol.vaddr);
|
||||
// expCause = False;
|
||||
// allowCapPTE = True;
|
||||
|
||||
Maybe#(Trap) cause = Invalid;
|
||||
if (expCause matches tagged Valid .c) cause = Valid(Exception(c));
|
||||
|
||||
@@ -754,6 +774,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
|
||||
$display("KONATAS\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id);
|
||||
$fflush;
|
||||
`endif
|
||||
// Try me!
|
||||
// if (x.mem_func == St) begin
|
||||
// paddr = 256;
|
||||
// end
|
||||
|
||||
// update LSQ
|
||||
LSQUpdateAddrResult updRes <- lsq.updateAddr(
|
||||
x.ldstq_tag, cause, x.allowCapLoad && allowCapPTE, paddr, isMMIO, x.shiftedBE
|
||||
|
||||
@@ -144,7 +144,7 @@ typedef union tagged {
|
||||
module mkDTlb#(
|
||||
function TlbReq getTlbReq(instT inst)
|
||||
)(DTlb::DTlb#(instT)) provisos(Bits#(instT, a__));
|
||||
Bool verbose = False;
|
||||
Bool verbose = True;
|
||||
|
||||
// TLB array
|
||||
DTlbArray tlb <- mkDTlbArray;
|
||||
@@ -562,6 +562,7 @@ module mkDTlb#(
|
||||
// bare mode
|
||||
pendWait[idx] <= None;
|
||||
pendResp[idx] <= tuple3(r.addr, Invalid, True);
|
||||
$display("bare mode");
|
||||
if(verbose) $display("DTLB %m req (bare): ", fshow(r));
|
||||
end
|
||||
|
||||
|
||||
@@ -1,647 +0,0 @@
|
||||
// Copyright (c) 2017 Massachusetts Institute of Technology
|
||||
//
|
||||
//-
|
||||
// RVFI_DII + CHERI modifications:
|
||||
// Copyright (c) 2020 Alexandre Joannou
|
||||
// Copyright (c) 2020 Peter Rugg
|
||||
// Copyright (c) 2020 Jonathan Woodruff
|
||||
// Copyright (c) 2021 Marno van der Maas
|
||||
// All rights reserved.
|
||||
//
|
||||
// This software was developed by SRI International and the University of
|
||||
// Cambridge Computer Laboratory (Department of Computer Science and
|
||||
// Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
|
||||
// DARPA SSITH research programme.
|
||||
//
|
||||
// This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet").
|
||||
//-
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person
|
||||
// obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without
|
||||
// restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
// of the Software, and to permit persons to whom the Software is
|
||||
// furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be
|
||||
// included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
// SOFTWARE.
|
||||
|
||||
`include "ProcConfig.bsv"
|
||||
|
||||
import Types::*;
|
||||
import ProcTypes::*;
|
||||
import Vector::*;
|
||||
import CHERICap::*;
|
||||
import CHERICC_Fat::*;
|
||||
import ISA_Decls_CHERI::*;
|
||||
import CacheUtils::*; // For CLoadTags alignment
|
||||
|
||||
(* noinline *)
|
||||
function Maybe#(CSR_XCapCause) capChecksExec(CapPipe a, CapPipe b, CapPipe ddc, CapChecks toCheck, ImmData imm);
|
||||
function Maybe#(CSR_XCapCause) e1(CHERIException e) = Valid(CSR_XCapCause{cheri_exc_reg: toCheck.rn1, cheri_exc_code: e});
|
||||
function Maybe#(CSR_XCapCause) e2(CHERIException e) = Valid(CSR_XCapCause{cheri_exc_reg: toCheck.rn2, cheri_exc_code: e});
|
||||
function Maybe#(CSR_XCapCause) eDDC(CHERIException e) = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1, pack(scrAddrDDC)}, cheri_exc_code: e});
|
||||
Maybe#(CSR_XCapCause) result = Invalid;
|
||||
if (toCheck.src1_tag && !isValidCap(a))
|
||||
result = e1(cheriExcTagViolation);
|
||||
else if (toCheck.src2_tag && !isValidCap(b))
|
||||
result = e2(cheriExcTagViolation);
|
||||
else if (toCheck.src1_unsealed_or_sentry && isValidCap(a) && (getKind(a) != UNSEALED) && (getKind(a) != SENTRY))
|
||||
result = e1(cheriExcSealViolation);
|
||||
else if (toCheck.src1_unsealed_or_imm_zero && isValidCap(a) && (getKind(a) != UNSEALED) && (imm != 0))
|
||||
result = e1(cheriExcSealViolation);
|
||||
else if (toCheck.src1_sealed_with_type && (getKind (a) matches tagged SEALED_WITH_TYPE .t ? False : True))
|
||||
result = e1(cheriExcSealViolation);
|
||||
else if (toCheck.src2_sealed_with_type && (getKind (b) matches tagged SEALED_WITH_TYPE .t ? False : True))
|
||||
result = e2(cheriExcSealViolation);
|
||||
else if (toCheck.src1_type_not_reserved && !validAsType(a, zeroExtend(getKind(a).SEALED_WITH_TYPE)))
|
||||
result = e1(cheriExcTypeViolation);
|
||||
else if (toCheck.src1_src2_types_match && getKind(a).SEALED_WITH_TYPE != getKind(b).SEALED_WITH_TYPE)
|
||||
result = e1(cheriExcTypeViolation);
|
||||
else if (toCheck.src1_permit_ccall && !getHardPerms(a).permitCCall)
|
||||
result = e1(cheriExcPermitCCallViolation);
|
||||
else if (toCheck.src2_permit_ccall && !getHardPerms(b).permitCCall)
|
||||
result = e2(cheriExcPermitCCallViolation);
|
||||
else if (toCheck.src1_permit_x && !getHardPerms(a).permitExecute)
|
||||
result = e1(cheriExcPermitXViolation);
|
||||
else if (toCheck.src2_no_permit_x && getHardPerms(b).permitExecute)
|
||||
result = e2(cheriExcPermitXViolation);
|
||||
return result;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Maybe#(CSR_XCapCause) capChecksMem(CapPipe auth, CapPipe data, CapChecks toCheck, MemFunc mem_func, ByteOrTagEn byteOrTagEn);
|
||||
function Maybe#(CSR_XCapCause) eAuth(CHERIException e) = Valid(CSR_XCapCause{cheri_exc_reg: case (toCheck.check_authority_src) matches Src1: toCheck.rn1;
|
||||
Ddc: {1'b1, pack(scrAddrDDC)};
|
||||
endcase
|
||||
, cheri_exc_code: e});
|
||||
Maybe#(CSR_XCapCause) result = Invalid;
|
||||
match {.isLoad, .isStore} = case (mem_func)
|
||||
Ld, Lr: tuple2(True, False);
|
||||
St, Sc: tuple2(False, True);
|
||||
Amo: tuple2(True, True);
|
||||
endcase;
|
||||
Bool storeValidCap = isStore && isValidCap(data) && byteOrTagEn == DataMemAccess(replicate(True));
|
||||
if (!isValidCap(auth))
|
||||
result = eAuth(cheriExcTagViolation);
|
||||
else if (getKind(auth) != UNSEALED)
|
||||
result = eAuth(cheriExcSealViolation);
|
||||
else if (isLoad && !getHardPerms(auth).permitLoad)
|
||||
result = eAuth(cheriExcPermitRViolation);
|
||||
else if (isLoad && !getHardPerms(auth).permitLoadCap && byteOrTagEn == TagMemAccess)
|
||||
result = eAuth(cheriExcPermitRCapViolation);
|
||||
else if (isStore && !getHardPerms(auth).permitStore)
|
||||
result = eAuth(cheriExcPermitWViolation);
|
||||
else if (storeValidCap && !getHardPerms(auth).permitStoreCap)
|
||||
result = eAuth(cheriExcPermitWCapViolation);
|
||||
else if (storeValidCap && !getHardPerms(auth).permitStoreLocalCap && !getHardPerms(data).global)
|
||||
result = eAuth(cheriExcPermitWLocalCapViolation);
|
||||
return result;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Maybe#(BoundsCheck) prepareBoundsCheck(CapPipe a, CapPipe b, CapPipe pcc,
|
||||
CapPipe ddc, Data vaddr, Bit#(TAdd#(CacheUtils::LogCLineNumMemDataBytes,1)) size, // These two are only used in the memory pipe. May factor into two functions later.
|
||||
CapChecks toCheck);
|
||||
BoundsCheck ret = ?;
|
||||
CapPipe authority = ?;
|
||||
case(toCheck.check_authority_src)
|
||||
Src1: begin
|
||||
authority = a;
|
||||
ret.authority_idx = toCheck.rn1;
|
||||
end
|
||||
Src2: begin
|
||||
authority = b;
|
||||
ret.authority_idx = toCheck.rn2;
|
||||
end
|
||||
Pcc: begin
|
||||
authority = pcc;
|
||||
ret.authority_idx = {1'b1, pack(scrAddrPCC)};
|
||||
end
|
||||
Ddc: begin
|
||||
authority = ddc;
|
||||
ret.authority_idx = {1'b1, pack(scrAddrDDC)};
|
||||
end
|
||||
endcase
|
||||
ret.authority_base = getBase(authority);
|
||||
ret.authority_top = getTop(authority);
|
||||
|
||||
case(toCheck.check_low_src)
|
||||
Src1Addr: ret.check_low = getAddr(a);
|
||||
Src1Base: ret.check_low = getBase(a);
|
||||
Src1Type: ret.check_low = zeroExtend(getKind(a).SEALED_WITH_TYPE);
|
||||
Src2Addr: ret.check_low = getAddr(b);
|
||||
Vaddr: ret.check_low = vaddr;
|
||||
endcase
|
||||
|
||||
case(toCheck.check_high_src)
|
||||
Src1AddrPlus2: ret.check_high = {1'b0,getAddr(a)+2};
|
||||
Src1Top: ret.check_high = getTop(a);
|
||||
Src1Type: ret.check_high = zeroExtend(getKind(a).SEALED_WITH_TYPE);
|
||||
Src2Addr: ret.check_high = {1'b0,getAddr(b)};
|
||||
ResultTop: ret.check_high = {1'b0,getAddr(a)} + {1'b0,getAddr(b)};
|
||||
VaddrPlusSize: ret.check_high = {1'b0,vaddr} + zeroExtend(size);
|
||||
endcase
|
||||
|
||||
ret.check_inclusive = toCheck.check_inclusive;
|
||||
if (toCheck.check_enable) return Valid(ret);
|
||||
else return Invalid;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Data alu(Data a, Data b, AluFunc func);
|
||||
Data res = (case(func)
|
||||
Add : (a + b);
|
||||
Addw : signExtend((a + b)[31:0]);
|
||||
Sub : (a - b);
|
||||
Subw : signExtend((a[31:0] - b[31:0])[31:0]);
|
||||
And : (a & b);
|
||||
Or : (a | b);
|
||||
Xor : (a ^ b);
|
||||
Slt : zeroExtend( pack( signedLT(a, b) ) );
|
||||
Sltu : zeroExtend( pack( a < b ) );
|
||||
Sll : (a << b[5:0]);
|
||||
Sllw : signExtend((a[31:0] << b[4:0])[31:0]);
|
||||
Srl : (a >> b[5:0]);
|
||||
Sra : signedShiftRight(a, b[5:0]);
|
||||
Srlw : signExtend((a[31:0] >> b[4:0])[31:0]);
|
||||
Sraw : signExtend(signedShiftRight(a[31:0], b[4:0])[31:0]);
|
||||
Csrw : b;
|
||||
Csrs : (a | b); // same as Or
|
||||
Csrc : (a & ~b);
|
||||
default : 0;
|
||||
endcase);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function CapPipe setBoundsALU(CapPipe cap, Data len, SetBoundsFunc boundsOp);
|
||||
let combinedResult = setBoundsCombined(cap, len);
|
||||
CapPipe res = (case (boundsOp) matches
|
||||
SetBoundsRounding: combinedResult.cap;
|
||||
SetBoundsExact: combinedResult.cap;
|
||||
CRRL: nullWithAddr(combinedResult.length);
|
||||
CRAM: nullWithAddr(combinedResult.mask);
|
||||
endcase);
|
||||
if (!combinedResult.inBounds) res = setValidCap(res, False);
|
||||
if (boundsOp == SetBoundsExact && !combinedResult.exact) res = setValidCap(res, False);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function CapPipe specialRWALU(CapPipe cap, CapPipe oldCap, SpecialRWFunc scrType);
|
||||
function csrOp (oldAddr, val, f) =
|
||||
case (f)
|
||||
Write: val;
|
||||
Set: (oldAddr | val);
|
||||
Clear: (oldAddr & ~val);
|
||||
endcase;
|
||||
let addr = getAddr(cap);
|
||||
let oldAddr = getAddr(oldCap);
|
||||
CapPipe res = (case (scrType) matches
|
||||
tagged TVEC .csrf: update_scr_via_csr(oldCap, csrOp(oldAddr, getAddr(cap), csrf) & ~64'h2, False);
|
||||
tagged EPC .csrf: update_scr_via_csr(oldCap, csrOp(oldAddr, getAddr(cap), csrf) & ~64'h1, False);
|
||||
tagged TCC: update_scr_via_csr(cap, addr & ~64'h2, False); // Mask out bit 1
|
||||
tagged EPCC: update_scr_via_csr(cap, addr & ~64'h1, addr[0] == 1'b0); // Mask out bit 0
|
||||
tagged Normal: cap;
|
||||
endcase);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
function Tuple2#(Data, Bool) extractType(CapPipe a);
|
||||
if (getKind(a) == UNSEALED) return tuple2(otype_unsealed_ext, True);
|
||||
else if (getKind(a) == SENTRY ) return tuple2(otype_sentry_ext, True);
|
||||
else if (getKind(a) == RES0 ) return tuple2(otype_res0_ext, True);
|
||||
else if (getKind(a) == RES1 ) return tuple2(otype_res1_ext, True);
|
||||
else return tuple2(zeroExtend(getKind(a).SEALED_WITH_TYPE), False);
|
||||
endfunction
|
||||
|
||||
function CapPipe clearTagIf(CapPipe a, Bool cond);
|
||||
return setValidCap(a, isValidCap(a) && !cond);
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func);
|
||||
let a_mut = setValidCap(a, isValidCap(a) && getKind(a) == UNSEALED);
|
||||
let b_mut = setValidCap(b, isValidCap(b) && getKind(b) == UNSEALED);
|
||||
match {.a_type, .a_res} = extractType(a);
|
||||
Bool sealPassthrough = !isValidCap(b) || getKind(a) != UNSEALED || !isInBounds(b, False) || getAddr(b) == otype_unsealed_ext;
|
||||
Bool sealIllegal = getKind(b) != UNSEALED || !getHardPerms(b).permitSeal || !validAsType(b, getAddr(b));
|
||||
let new_hard_perms = getHardPerms(a);
|
||||
new_hard_perms.global = new_hard_perms.global && getHardPerms(b).global;
|
||||
Bool unsealIllegal = !isValidCap(b) || getKind(b) != UNSEALED || getKind(a) == UNSEALED || a_res || getAddr(b) != a_type || !getHardPerms(b).permitUnseal || !isInBounds(b, False);
|
||||
Bool buildCapIllegal = !isValidCap(b) || getKind(b) != UNSEALED || !isDerivable(a) || (getPerms(a) & getPerms(b)) != getPerms(a) || getBase(a) < getBase(b) || getTop(a) > getTop(b); // XXX needs optimisation
|
||||
CapPipe res = (case(func) matches
|
||||
tagged ModifyOffset .offsetOp :
|
||||
modifyOffset(a_mut, getAddr(b), offsetOp == IncOffset).value;
|
||||
tagged SetBounds .boundsOp :
|
||||
setBoundsALU(a_mut, getAddr(b), boundsOp);
|
||||
tagged SpecialRW .scrType :
|
||||
case (scrType) matches
|
||||
tagged TCC: b;
|
||||
tagged EPCC: b;
|
||||
tagged Normal: b;
|
||||
tagged TVEC ._: nullWithAddr(getAddr(b));
|
||||
tagged EPC ._: nullWithAddr(getAddr(b));
|
||||
endcase
|
||||
tagged SetAddr .addrSource :
|
||||
clearTagIf(setAddr(b_mut, (addrSource == Src1Type) ? a_type : getAddr(a) ).value, (addrSource == Src1Type) ? a_res : False);
|
||||
tagged SealEntry :
|
||||
setKind(a_mut, SENTRY);
|
||||
tagged Seal :
|
||||
clearTagIf( setKind(a_mut, SEALED_WITH_TYPE (truncate(getAddr(b))))
|
||||
, sealPassthrough || sealIllegal);
|
||||
tagged CSeal :
|
||||
(sealPassthrough ? a :
|
||||
clearTagIf(setKind(a_mut, SEALED_WITH_TYPE (truncate(getAddr(b)))), sealIllegal));
|
||||
tagged Unseal .src :
|
||||
clearTagIf(setHardPerms(setKind(((src == Src1) ? a:b), UNSEALED), new_hard_perms), (src == Src1) && unsealIllegal);
|
||||
tagged AndPerm :
|
||||
setPerms(a_mut, pack(getPerms(a)) & truncate(getAddr(b)));
|
||||
tagged SetFlags :
|
||||
setFlags(a_mut, truncate(getAddr(b)));
|
||||
tagged FromPtr :
|
||||
(getAddr(a) == 0 ? nullCap : setAddr(b_mut, getAddr(a)).value);
|
||||
tagged SetHigh:
|
||||
fromMem(tuple2(False, {getAddr(b), getAddr(a)}));
|
||||
tagged BuildCap :
|
||||
setKind(setValidCap(a_mut, !buildCapIllegal), getKind(a)==SENTRY ? SENTRY : UNSEALED);
|
||||
tagged Move :
|
||||
a;
|
||||
tagged ClearTag :
|
||||
setValidCap(a, False);
|
||||
default: ?;
|
||||
endcase);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Data capInspect(CapPipe a, CapPipe b, CapInspectFunc func);
|
||||
Data res = (case(func) matches
|
||||
tagged TestSubset :
|
||||
// TODO will be bad for timing. Would like to reuse bounds check
|
||||
zeroExtend(pack( (isValidCap(b) == isValidCap(a))
|
||||
&& ((getPerms(a) & getPerms(b)) == getPerms(a))
|
||||
&& (getBase(a) >= getBase(b))
|
||||
&& (getTop(a) <= getTop(b))));
|
||||
tagged SetEqualExact :
|
||||
zeroExtend(pack(toMem(a) == toMem(b)));
|
||||
tagged GetLen :
|
||||
truncate(getLength(a));
|
||||
tagged GetBase :
|
||||
getBase(a);
|
||||
tagged GetTag :
|
||||
zeroExtend(pack(isValidCap(a)));
|
||||
tagged GetSealed :
|
||||
zeroExtend(pack(getKind(a) != UNSEALED));
|
||||
tagged GetAddr :
|
||||
getAddr(a);
|
||||
tagged GetOffset :
|
||||
getOffset(a);
|
||||
tagged GetFlags :
|
||||
zeroExtend(getFlags(a));
|
||||
tagged GetPerm :
|
||||
zeroExtend(getPerms(a));
|
||||
tagged GetHigh :
|
||||
zeroExtend(tpl_2(toMem(a))[127:64]);
|
||||
tagged GetType :
|
||||
tpl_1(extractType(a));
|
||||
tagged ToPtr :
|
||||
(isValidCap(a) ? getAddr(a) - getBase(b) : 0);
|
||||
default: ?;
|
||||
endcase);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
function CapPipe capALU(CapPipe a, CapPipe b, CapFunc func);
|
||||
CapPipe res = (case (func) matches
|
||||
tagged CapInspect .x:
|
||||
nullWithAddr(capInspect(a,b,func.CapInspect));
|
||||
default:
|
||||
capModify(a,b,func.CapModify);
|
||||
endcase);
|
||||
return res;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Bool aluBr(Data a, Data b, BrFunc brFunc);
|
||||
Bool brTaken = (case(brFunc)
|
||||
Eq : (a == b);
|
||||
Neq : (a != b);
|
||||
Lt : signedLT(a, b);
|
||||
Ltu : (a < b);
|
||||
Ge : signedGE(a, b);
|
||||
Geu : (a >= b);
|
||||
AT : True;
|
||||
NT : False;
|
||||
default : False;
|
||||
endcase);
|
||||
return brTaken;
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function CapPipe brAddrCalc(CapPipe pc, CapPipe val, IType iType, Data imm, Bool taken, Bit #(32) orig_inst, Bool cap);
|
||||
CapPipe pcPlusN = addPc(pc, ((orig_inst [1:0] == 2'b11) ? 4 : 2));
|
||||
|
||||
//if (!cap) val = setOffset(pc, getAddr(val)).value;
|
||||
//CapPipe branchTarget = incOffset(pc, imm).value;
|
||||
//CapPipe jumpTarget = incOffset(val, imm).value;
|
||||
|
||||
CapPipe nextPc = pc;
|
||||
Data offset = imm;
|
||||
Bool doInc = True;
|
||||
if (iType==Jr || iType==CCall || iType ==CJALR) begin
|
||||
if (cap) nextPc = val;
|
||||
else begin
|
||||
offset = getAddr(val) + imm;
|
||||
doInc = False;
|
||||
end
|
||||
end
|
||||
CapPipe targetAddr = ?;
|
||||
if(doInc) targetAddr = modifyOffset(nextPc, offset, doInc).value;
|
||||
else targetAddr = setAddr(nextPc, offset).value;
|
||||
// jumpTarget.address[0] = 1'b0;
|
||||
targetAddr = setAddrUnsafe(targetAddr, {truncateLSB(getAddr(targetAddr)), 1'b0});
|
||||
targetAddr = setKind(targetAddr, UNSEALED); // It is checked elsewhere that we have an unsealed cap already, or sentry if permitted
|
||||
|
||||
return (case (iType)
|
||||
J, CJAL, Jr, CCall, CJALR: targetAddr;
|
||||
Br : (taken ? targetAddr : pcPlusN);
|
||||
default : pcPlusN;
|
||||
endcase);
|
||||
endfunction
|
||||
/*
|
||||
(* noinline *)
|
||||
function ControlFlow getControlFlow(DecodedInst dInst, Data rVal1, Data rVal2, Addr pc, Addr ppc, Bit #(32) orig_inst);
|
||||
ControlFlow cf = unpack(0);
|
||||
|
||||
Bool taken = dInst.execFunc matches tagged Br .br_f ? aluBr(rVal1, rVal2, br_f) : False;
|
||||
Addr nextPc = brAddrCalc(pc, rVal1, dInst.iType, validValue(getDInstImm(dInst)), taken, orig_inst);
|
||||
Bool mispredict = nextPc != ppc;
|
||||
|
||||
cf.pc = pc;
|
||||
cf.nextPc = nextPc;
|
||||
cf.taken = taken;
|
||||
cf.mispredict = mispredict;
|
||||
|
||||
return cf;
|
||||
endfunction
|
||||
*/
|
||||
(* noinline *)
|
||||
function ExecResult basicExec(DecodedInst dInst, CapPipe rVal1, CapPipe rVal2, CapPipe pcc, CapPipe ppc, Bit #(32) orig_inst);
|
||||
// just data, addr, and control flow
|
||||
CapPipe data = nullCap;
|
||||
CapPipe addr = nullCap;
|
||||
|
||||
Bool newPcc = dInst.iType == CJALR || dInst.iType == CCall;
|
||||
ControlFlow cf = ControlFlow{pc: pcc, nextPc: nullCap, taken: False, newPcc: newPcc, mispredict: False};
|
||||
|
||||
Maybe#(CapPipe) capImm = isValid(getDInstImm(dInst)) ? Valid (nullWithAddr(getDInstImm(dInst).Valid)) : Invalid;
|
||||
let aluVal2 = dInst.capFunc matches tagged CapModify .cm &&& cm matches tagged SpecialRW ._ ? rVal2 : fromMaybe(rVal2, capImm);
|
||||
// Get the alu function. By default, it adds. This is used by memory instructions
|
||||
AluFunc alu_f = dInst.execFunc matches tagged Alu .alu_f ? alu_f : Add;
|
||||
Data alu_result = alu(getAddr(rVal1), getAddr(aluVal2), alu_f);
|
||||
|
||||
CapPipe cap_alu_result = capALU(rVal1, aluVal2, dInst.capFunc);
|
||||
CapPipe link_pcc = addPc(pcc, ((orig_inst [1:0] == 2'b11) ? 4 : 2));
|
||||
|
||||
// Default branch function is not taken
|
||||
BrFunc br_f = dInst.execFunc matches tagged Br .br_f ? br_f : NT;
|
||||
cf.taken = aluBr(getAddr(rVal1), getAddr(rVal2), br_f);
|
||||
cf.nextPc = brAddrCalc(pcc, rVal1, dInst.iType, fromMaybe(0,getDInstImm(dInst)), cf.taken, orig_inst, newPcc);
|
||||
|
||||
Maybe#(CSR_XCapCause) capException = capChecksExec(rVal1, aluVal2, nullCap, dInst.capChecks, dInst.imm.Valid);
|
||||
if (dInst.execFunc matches tagged Br .unused) begin
|
||||
rVal1 = cf.nextPc;
|
||||
if (!cf.taken) dInst.capChecks.check_enable = False;
|
||||
end
|
||||
Maybe#(BoundsCheck) boundsCheck = prepareBoundsCheck(rVal1, aluVal2, pcc,
|
||||
nullCap, 0, 0, // These three are only used in the memory pipe
|
||||
dInst.capChecks);
|
||||
|
||||
cf.nextPc = setKind(cf.nextPc, UNSEALED);
|
||||
cf.mispredict = cf.nextPc != ppc;
|
||||
|
||||
data = (case (dInst.iType)
|
||||
St : rVal2;
|
||||
Sc : rVal2;
|
||||
Amo : rVal2;
|
||||
J : nullWithAddr(getAddr(link_pcc));
|
||||
CJAL : setKind(link_pcc, SENTRY);
|
||||
CCall : cap_alu_result;
|
||||
CJALR : setKind(link_pcc, SENTRY);
|
||||
Jr : nullWithAddr(getAddr(link_pcc));
|
||||
Auipc : nullWithAddr(getAddr(pcc) + getDInstImm(dInst).Valid);
|
||||
Auipcc : incOffset(pcc, getDInstImm(dInst).Valid).value; // could be computed with alu
|
||||
Csr : rVal1;
|
||||
Scr : cap_alu_result;
|
||||
Cap : cap_alu_result;
|
||||
default : nullWithAddr(alu_result);
|
||||
endcase);
|
||||
CapMem csr_data = (case (dInst.iType)
|
||||
Scr: cast(specialRWALU(fromMaybe(rVal1, capImm), rVal2, dInst.capFunc.CapModify.SpecialRW));
|
||||
default: nullWithAddr(alu_result);
|
||||
endcase);
|
||||
addr = (case (dInst.iType)
|
||||
Ld, St, Lr, Sc, Amo : nullWithAddr(alu_result);
|
||||
default : cf.nextPc; //TODO should this be nullified?
|
||||
endcase);
|
||||
|
||||
return ExecResult{data: data, csrData: csr_data, addr: addr, controlFlow: cf, capException: capException, boundsCheck: boundsCheck};
|
||||
endfunction
|
||||
|
||||
(* noinline *)
|
||||
function Maybe#(Trap) checkForException(
|
||||
DecodedInst dInst,
|
||||
ArchRegs regs,
|
||||
CsrDecodeInfo csrState,
|
||||
CapMem pcc,
|
||||
Bool fourByteInst
|
||||
); // regs needed to check if x0 is a src
|
||||
Maybe#(Trap) exception = Invalid;
|
||||
let prv = csrState.prv;
|
||||
|
||||
if(dInst.iType == Ecall) begin
|
||||
exception = Valid (Exception (case(prv)
|
||||
prvU: excEnvCallU;
|
||||
prvS: excEnvCallS;
|
||||
prvM: excEnvCallM;
|
||||
default: excIllegalInst;
|
||||
endcase));
|
||||
end
|
||||
else if(dInst.iType == Ebreak) begin
|
||||
exception = Valid (Exception (excBreakpoint));
|
||||
end
|
||||
else if(dInst.iType == Mret) begin
|
||||
if(prv < prvM) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
else if (!getHardPerms(pcc).accessSysRegs) begin
|
||||
exception = Valid (CapException (CSR_XCapCause {cheri_exc_reg: {1'b1, pack(scrAddrPCC)}, cheri_exc_code: cheriExcPermitASRViolation}));
|
||||
end
|
||||
end
|
||||
else if(dInst.iType == Sret) begin
|
||||
if(prv < prvS) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
else if(prv == prvS && csrState.trapSret) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
else if (!getHardPerms(pcc).accessSysRegs) begin
|
||||
exception = Valid (CapException (CSR_XCapCause {cheri_exc_reg: {1'b1, pack(scrAddrPCC)}, cheri_exc_code: cheriExcPermitASRViolation}));
|
||||
end
|
||||
end
|
||||
else if(dInst.iType == SFence) begin
|
||||
if(prv == prvS && csrState.trapVM) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
end
|
||||
else if(dInst.iType == Csr) begin
|
||||
let csr = pack(fromMaybe(csrAddrNone, dInst.csr));
|
||||
Bool csr_has_priv = (prv >= csr[9:8]);
|
||||
if(!csr_has_priv) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
else if(prv == prvS && csrState.trapVM &&
|
||||
validValue(dInst.csr) == csrAddrSATP) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
let rs1 = case (regs.src2) matches
|
||||
tagged Valid (tagged Gpr .r) : r;
|
||||
default: 0;
|
||||
endcase;
|
||||
let imm = case (dInst.imm) matches
|
||||
tagged Valid .n: n;
|
||||
default: 0;
|
||||
endcase;
|
||||
Bool writes_csr = ((dInst.execFunc == tagged Alu Csrw) || (rs1 != 0) || (imm != 0));
|
||||
Bool read_only = (csr [11:10] == 2'b11);
|
||||
Bool write_deny = (writes_csr && read_only);
|
||||
Bool asr_allow = getHardPerms(pcc).accessSysRegs
|
||||
|| ((pack(csrAddrHPMCOUNTER3) <= csr) && (csr <= pack(csrAddrHPMCOUNTER31)) && !writes_csr)
|
||||
|| (csr == pack(csrAddrFFLAGS))
|
||||
|| (csr == pack(csrAddrFRM))
|
||||
|| (csr == pack(csrAddrFCSR))
|
||||
|| (csr == pack(csrAddrCYCLE) && !writes_csr)
|
||||
|| (csr == pack(csrAddrTIME) && !writes_csr)
|
||||
|| (csr == pack(csrAddrINSTRET) && !writes_csr);
|
||||
Bool unimplemented = (csr == pack(csrAddrNone)); // Added by Bluespec
|
||||
if (write_deny || !csr_has_priv || unimplemented) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end else if (!asr_allow) begin
|
||||
exception = Valid (CapException (CSR_XCapCause {cheri_exc_reg: {1'b1, pack(scrAddrPCC)}, cheri_exc_code: cheriExcPermitASRViolation}));
|
||||
end
|
||||
end
|
||||
else if(dInst.scr matches tagged Valid .scr) begin
|
||||
Bool scr_has_priv = (prv >= pack(scr)[4:3]);
|
||||
Bool unimplemented = (scr == scrAddrNone);
|
||||
Bool writes_scr = regs.src1 == Valid (tagged Gpr 0) ? False : True;
|
||||
Bool read_only = (scr == scrAddrPCC);
|
||||
Bool write_deny = (writes_scr && read_only);
|
||||
Bool asr_allow = getHardPerms(pcc).accessSysRegs ||
|
||||
scr == scrAddrDDC || scr == scrAddrPCC;
|
||||
if(!scr_has_priv || unimplemented || write_deny) begin
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end else if (!asr_allow) begin
|
||||
exception = Valid (CapException (CSR_XCapCause {cheri_exc_reg: {1'b1, pack(scrAddrPCC)}, cheri_exc_code: cheriExcPermitASRViolation}));
|
||||
end
|
||||
end
|
||||
else if(dInst.iType == Fpu) begin
|
||||
if(dInst.execFunc matches tagged Fpu .fpu_f) begin
|
||||
// Get rounding mode
|
||||
let rm = (fpu_f.rm == rmRDyn) ? unpack(csrState.frm) : fpu_f.rm;
|
||||
case(rm)
|
||||
rmRNE, rmRTZ, rmRDN, rmRUP, rmRMM: exception = exception; // legal modes
|
||||
default : exception = Valid (Exception (excIllegalInst));
|
||||
endcase
|
||||
end
|
||||
else begin
|
||||
// Fpu instruction without FPU execFunc
|
||||
exception = Valid (Exception (excIllegalInst));
|
||||
end
|
||||
end
|
||||
|
||||
// Check that the end of the instruction is in bounds of PCC.
|
||||
CapPipe pcc_end = cast(addPc(pcc, (fourByteInst?4:2)));
|
||||
CapPipe pcc_start = cast(pcc);
|
||||
Maybe#(CSR_XCapCause) capException = Invalid;
|
||||
if (!isValidCap(pcc_start)) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(scrAddrPCC)}, cheri_exc_code: cheriExcTagViolation});
|
||||
if (getKind(pcc_start) != UNSEALED) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(scrAddrPCC)}, cheri_exc_code: cheriExcSealViolation});
|
||||
if (!getHardPerms(pcc_start).permitExecute) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(scrAddrPCC)}, cheri_exc_code: cheriExcPermitXViolation});
|
||||
if (!isInBounds(pcc_end, True)) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(scrAddrPCC)}, cheri_exc_code: cheriExcLengthViolation});
|
||||
if (!isInBounds(pcc_start, True)) capException = Valid(CSR_XCapCause{cheri_exc_reg: {1'b1,pack(scrAddrPCC)}, cheri_exc_code: cheriExcLengthViolation});
|
||||
|
||||
Maybe#(Trap) retval = Invalid;
|
||||
if (capException matches tagged Valid .ce) retval = Valid(CapException(ce));
|
||||
else retval = exception;
|
||||
|
||||
return retval;
|
||||
endfunction
|
||||
|
||||
// check mem access misaligned: byteEn is unshifted (just from Decode)
|
||||
function Bool memAddrMisaligned(Addr addr, ByteOrTagEn byteOrTagEn);
|
||||
MemDataByteEn byteEn = byteOrTagEn.DataMemAccess;
|
||||
if (byteOrTagEn == TagMemAccess) begin
|
||||
return(!isCLineAlignAddr(addr));
|
||||
end
|
||||
else if(byteEn[15]) begin
|
||||
return addr[3:0] != 0;
|
||||
end
|
||||
else if(byteEn[7]) begin
|
||||
return addr[2:0] != 0;
|
||||
end
|
||||
else if(byteEn[3]) begin
|
||||
return addr[1:0] != 0;
|
||||
end
|
||||
else if(byteEn[1]) begin
|
||||
return addr[0] != 0;
|
||||
end
|
||||
else begin
|
||||
return False;
|
||||
end
|
||||
endfunction
|
||||
|
||||
function MemTaggedData gatherLoad( Addr addr, ByteOrTagEn byteOrTagEn
|
||||
, Bool unsignedLd, MemTaggedData data);
|
||||
function extend = unsignedLd ? zeroExtend : signExtend;
|
||||
Bit#(IndxShamt) offset = truncate(addr);
|
||||
|
||||
MemDataByteEn byteEn = byteOrTagEn.DataMemAccess;
|
||||
if((byteOrTagEn == TagMemAccess) || pack(byteEn) == ~0) return data;
|
||||
else if(byteEn[7]) begin
|
||||
Vector#(2, Bit#(64)) dataVec = unpack(pack(data.data));
|
||||
return dataToMemTaggedData(extend(dataVec[offset[3]]));
|
||||
end else if(byteEn[3]) begin
|
||||
Vector#(4, Bit#(32)) dataVec = unpack(pack(data.data));
|
||||
return dataToMemTaggedData(extend(dataVec[offset[3:2]]));
|
||||
end else if(byteEn[1]) begin
|
||||
Vector#(8, Bit#(16)) dataVec = unpack(pack(data.data));
|
||||
return dataToMemTaggedData(extend(dataVec[offset[3:1]]));
|
||||
end else begin
|
||||
Vector#(16, Bit#(8)) dataVec = unpack(pack(data.data));
|
||||
return dataToMemTaggedData(extend(dataVec[offset]));
|
||||
end
|
||||
endfunction
|
||||
|
||||
function Tuple2#(ByteEn, Data) scatterStore(Addr addr, ByteEn byteEn, Data data);
|
||||
Bit#(IndxShamt) offset = truncate(addr);
|
||||
if(byteEn[7]) begin
|
||||
return tuple2(byteEn, data);
|
||||
end else if(byteEn[3]) begin
|
||||
return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});
|
||||
end else if(byteEn[1]) begin
|
||||
return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});
|
||||
end else begin
|
||||
return tuple2(unpack(pack(byteEn) << (offset)), data << {(offset), 3'b0});
|
||||
end
|
||||
endfunction
|
||||
12
test.txt
12
test.txt
@@ -1,12 +0,0 @@
|
||||
Let me know if this message works well on behalf of all of us.
|
||||
|
||||
Hi Jan,
|
||||
This is a very small gesture from Jose, Mathews, Yukang and Akilan. We have transferred 200 pounds equally contributed by all of us. As you are moving in and settling into your new place, we hope this can help you and Samantha cover certain expenses like buying furniture or for your very efficient interrail travel pass in the near future.
|
||||
|
||||
We will definetely miss the german embassy in Slatefort. Happy new year in advance from all of us!
|
||||
|
||||
Regards,
|
||||
Jose, Mathews, Yukang and Akilan
|
||||
(Your UK representation of transportation
|
||||
reform)
|
||||
|
||||
Reference in New Issue
Block a user