22 Commits

Author SHA1 Message Date
Jonathan Woodruff
066289f8aa Work in progress.
Wd_Data is moved to 512 bits, and LLC_AXI4_Adapter is updated.
Lots of build errors now; a few have been resolved.
2022-11-10 13:51:12 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Peter Rugg
a6b39b58a1 Clean up prints 2022-03-11 10:24:39 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
Peter Rugg
cedb4c279d Ensure the MMIO platform issues aligned requests by changing the AXI4_Size field based on the byte enables 2021-01-31 17:34:35 +00:00
Peter Rugg
6a317d1a00 Prevent instruction fetch to unexpected devices 2020-07-10 17:35:06 +01:00
Peter Rugg
c406d357c9 Add CHERI+RVFI_DII grant codes and copyrights 2020-07-06 17:39:25 +01:00
jon
49e384ab2e Don't wedge when peripherals return write errors. 2020-06-25 14:58:51 +01:00
jon
af6e562c84 Deq the incoming request when sending a fast error response to a bad mapping. 2020-06-25 14:20:28 +01:00
jon
86e143a9f7 Changes that are much more likely to work for uncached memory accesses,
up to 128-bits.  I'm getting a lockup in simulation that I haven't
resolved yet, but the request looks ok.
2020-06-24 19:45:34 +01:00
jon
312d0316da Use updated Bluestuff library, and also support uncached 128-bit transactions through MMIO. 2020-06-24 11:57:43 +01:00
Alexandre Joannou
b70498e00a Try new types to hold capabilities 2020-04-30 14:07:37 +01:00
Alexandre Joannou
b5b2b4fe5c Port AXI4 changes from Flute 2020-03-27 16:45:26 +00:00
Jonathan Woodruff
2aa902f61a Change tabs to 8 spaces, this time being careful to do this only in BSV files. 2020-03-23 14:44:39 +00:00
Jonathan Woodruff
a6e5a7bff0 Revert "Fix whitespace in src_Core directory."
This reverts commit a137a6ede7.
2020-03-23 14:40:02 +00:00
Jonathan Woodruff
a137a6ede7 Fix whitespace in src_Core directory.
Replace all tabs with 8 spaces.
2020-03-23 14:28:00 +00:00
rsnikhil
fafd99c983 Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below)
PLIC: updated to latest version from Piccolo/Flute.

MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
    AXI4 fabrics. Writes that specify 8-byte size, but only write in
    upper or lower word using strobes, are converted into 4-byte size.

Core.bsv: added a notification to the Debug Module re. CPU halt.
2020-03-08 15:39:57 -04:00
rsnikhil
96a0897bf5 In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response.  Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
2020-02-28 14:07:45 -05:00
rsnikhil
83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00
rsnikhil
3d4960edc5 Bug fixes; now passing rv64mi-p-access ISA test
Modified
  src_Core/CPU/MMIO_AXI4_Adapter.bsv
    Instead of aborting on axi4 mem read error, pass the error on to the core
  src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
    Added mainMemBoundAddr
  src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv
    Update isMMIOAddr check to also check mainMemBoundAddr
  src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
    Update getFetchTarget to also check mainMemBoundAddr
    (still TODO: allow other IO addrs other than bootRom)
2019-04-10 12:42:23 -04:00
rsnikhil
9f94c9176e Added verbosity guards around $displays to dial down log verbosity
To get the instruction trace back, set verbosity to 1 in CommitStage.bsv.
Regressions: RV64ADFIMSU_Tooba_verilator: 199/227 PASS (1 test hangs)
2019-04-01 20:35:52 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00