Cheri-research/Toooba
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Author SHA1 Message Date
Jonathan Woodruff
be26ac9f79 Fix a typo in a comment. 2024-01-26 16:31:49 +00:00
Jonathan Woodruff
9baadf58f3 Tune the size of the fetch pipeline fifos. This appears to make a 3% 
performance improvement in CoreMark.
 2024-01-26 16:02:18 +00:00
Jonathan Woodruff
e873bbd553 Clean up Fetch stage optimisations. This includes removing references 
to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged
(Fetch3 is now Fetch2).
 2024-01-26 15:14:03 +00:00
Jonathan Woodruff
ca4e120a6c Use DReg instead of Reg, as intended. 2024-01-22 12:06:39 +00:00
Jonathan Woodruff
b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is 
going ahead.
 2024-01-22 11:38:52 +00:00
Jonathan Woodruff
640f330d7d Briefly report flush when vm_info has a change in the itlb to give an 
opportunity to flush the buffered translations.
 2024-01-19 11:48:04 +00:00
Jonathan Woodruff
d30bd71e72 Allow consuming TLB response while TLB is being flushed. 2024-01-18 13:04:21 +00:00
Jonathan Woodruff
83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. 2024-01-17 16:09:42 +00:00
Jonathan Woodruff
9d12fefda8 Remove commented-out code. 2024-01-17 14:30:34 +00:00
Jonathan Woodruff
829a787be5 Move to vector functions as it's cleaner. 2024-01-17 13:41:43 +00:00
Jonathan Woodruff
5a1ed7c57f Allow a vector of translations to be remembered. 
Just do 2 for now.
 2024-01-17 13:21:38 +00:00
Jonathan Woodruff
4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the 
proper TLB lookup if necessary.
 2024-01-16 17:00:10 +00:00
Jonathan Woodruff
eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. 2024-01-16 10:05:17 +00:00
Jonathan Woodruff
25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
 2024-01-16 09:50:35 +00:00
Jonathan Woodruff
f9bf4ad856 Use default value on reset of Map. 2024-01-15 17:00:00 +00:00
Jonathan Woodruff
2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. 2024-01-09 17:12:39 +00:00
Jonathan Woodruff
2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to 
doRegReadMem.
 2024-01-09 12:37:34 +00:00
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
8cd6e8db87 Bump BlueStuff 
This includes the changes to add wrappers for the delay shim. Unfortunately,
these are not directly suitable for the VCU118 setup since the uncached bus
needs to configure either itself or the cached bus, so leave those as is for
now
 2023-10-31 13:28:00 +00:00
gameboo
9dae87b505 Bump cheri-cap-lib 2023-10-31 13:28:00 +00:00
Peter Rugg
e9c2db4e60 Allocate mem_buf dynamically in elf_to_hex 
This hopefully fixes various compile issues due to having a > 2GB global
and also seems to have the size effect of running many times quicker.
 2023-10-25 13:35:32 +01:00
Simon Moore
d04c8ea3a9 Tidy section formatting so that it better exports to asciidoctor. 2023-08-30 18:26:47 +01:00
gameboo
da473192c7 Bump BlueStuff 2023-08-24 17:18:00 +01:00
gameboo
5ca4843be1 Bump BlueStuff 2023-08-21 14:30:26 +01:00
Peter Rugg
16592ae29a Bump BlueStuff 2023-08-16 18:30:27 +01:00
gameboo
43378ee339 Bump BlueStuff 2023-07-25 16:05:15 +01:00
Peter Rugg
4acbe2f43b Fix build error with SPEC contracts 2023-07-17 17:38:57 +01:00
Peter Rugg
5818a886dd Factor out delay shim 2023-07-15 22:37:45 +01:00
Peter Rugg
d509ab0fab Mask off address bits in latency shim 2023-07-15 22:37:45 +01:00
Peter Rugg
5414a13d3b Add prints for latency rules 2023-07-15 22:37:45 +01:00
Peter Rugg
f71f650023 Allow dynamic latency config 2023-07-15 22:37:45 +01:00
Peter Rugg
d17d3135bb Add error clear implementation for delayShim 2023-07-15 22:37:45 +01:00
Peter Rugg
23b471e0ae Increase number of outstanding transactions in delayShim 2023-07-15 22:37:45 +01:00
Peter Rugg
1a94699de6 Delay non-burst channels 2023-07-15 22:37:45 +01:00
Peter Rugg
e6370f46f6 Remove unnecessary type 2023-07-15 22:37:45 +01:00
Peter Rugg
f7755d0e58 Increase DRAM latency for realism 2023-07-15 22:37:45 +01:00
gameboo
2584c96095 Bump BlueStuff 2023-07-13 15:35:20 +01:00
gameboo
561683343d Add a mean to configure starting PC dynamically at start of simulation 2023-07-13 15:34:08 +01:00
gameboo
f00d924528 Bump BlueStuff 2023-07-04 17:08:16 +01:00
Peter Rugg
373b849d29 Merge branch 'tag-clear' into CHERI 2023-06-27 11:38:42 +01:00
Peter Rugg
ec4eacac9c Fix CSetAddr tag clear bug 2023-06-26 18:01:56 +01:00
Jonathan Woodruff
3ebf537f71 Tidy up tracing options, including using RVFI when building for bluesim 
(which I'm sure we had meant to be doing?).
 2023-06-23 13:09:38 +00:00
gameboo
c1f631eed3 Bump BlueStuff 2023-06-22 17:20:45 +01:00
gameboo
b3a75cfeac Bump BlueStuff and make use of Makefile fragment 2023-06-22 16:40:23 +01:00
gameboo
11d5d403ed Bump BlueStuff 2023-06-22 16:02:19 +01:00
gameboo
78b4554f5e Bump BlueStuff 2023-06-21 16:00:11 +01:00
Peter Rugg
86782f9bb5 Cleanup unused exception code 2023-06-20 16:46:39 +01:00