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190e84dfd1c3b71c320097349ac829160d55402a
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Author SHA1 Message Date
Jessica Clarke
190e84dfd1 .gitignore. Ignore .depends.mk files 2020-07-06 01:55:12 +01:00
Jessica Clarke
17ed2dfde8 Revert CACHE_SIZE back to LARGE 
The default was erroneously changed, causing P3 builds to have smaller
caches, so switch it back. The RVFI-DII builds override this with a TEST
configuration anyway now.
 2020-07-05 21:44:17 +01:00
Jessica Clarke
7b1259b41b Add a Bluesim RVFI-DII config 2020-07-05 21:43:21 +01:00
Jessica Clarke
badf5c8e37 Include xCHERI in ARCH and build directory names 
Also use RVFI_DII not RVFIDII in the directory names.

This makes everything match Piccolo/Flute rather than having Toooba be a
weird, inconsistent and plain wrong.
 2020-07-05 21:41:28 +01:00
Jessica Clarke
46ae8ea159 Port parallel build support to bluesim 2020-07-05 21:31:44 +01:00
Jessica Clarke
106f70e42b Fix Bluesim build (synced from Verilator Makefile) 2020-07-05 21:28:19 +01:00
Jessica Clarke
027b769904 Reduce diff to upstream 2020-07-05 21:28:12 +01:00
Jessica Clarke
0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl 
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
 2020-07-05 21:26:18 +01:00
Jessica Clarke
cd8e2a15ef Regenerate verilog 2020-07-02 03:00:55 +01:00
Jessica Clarke
1173cbb2c6 CsrFile.bsv: Actually respect CHERI fault delegation 
Also remove a dangerous default case item that masked this bug. It's
completely unnecessary upstream too and a bad idea.
 2020-07-02 02:44:09 +01:00
Peter Rugg
dcc506a365 Regenerate verilog 2020-07-01 17:08:08 +01:00
Peter Rugg
20e940eb66 Allow delegation of CHERI traps 2020-07-01 16:07:08 +01:00
Peter Rugg
9a00bde2b7 Revert accidentally making simulation memory uncached 2020-06-30 11:33:43 +01:00
Peter Rugg
f8972768a2 Regenerate verilog 2020-06-30 00:00:29 +01:00
Peter Rugg
c8e4a64128 Add sentries 2020-06-29 23:29:08 +01:00
Peter Rugg
70185dabac Allow debug access to SCR offsets 2020-06-29 23:27:23 +01:00
jon
e403240818 Undo gratuitous whitespace changes. 2020-06-26 11:25:46 +01:00
jon
004d039bd8 Reset the UART properly. 
Also move to non-synth interface for UART.
Also annoying whistespace changes to normalise tabs.
 2020-06-25 18:04:27 +01:00
Peter Rugg
258a0921e6 Regenerate verilog 2020-06-25 16:23:40 +01:00
jon
49e384ab2e Don't wedge when peripherals return write errors. 2020-06-25 14:58:51 +01:00
jon
af6e562c84 Deq the incoming request when sending a fast error response to a bad mapping. 2020-06-25 14:20:28 +01:00
Peter Rugg
a5578a715a Regenerate verilog 2020-06-24 21:16:57 +01:00
jon
86e143a9f7 Changes that are much more likely to work for uncached memory accesses, 
up to 128-bits.  I'm getting a lockup in simulation that I haven't
resolved yet, but the request looks ok.
 2020-06-24 19:45:34 +01:00
jon
312d0316da Use updated Bluestuff library, and also support uncached 128-bit transactions through MMIO. 2020-06-24 11:57:43 +01:00
jon
56cd502145 Bump bluestuff to recent version. This needs updates to the source. 2020-06-24 11:55:12 +01:00
jon
a51ddf17be Use the request ID in the response to the DMA interface. 2020-06-20 12:15:49 +01:00
Peter Rugg
7d866f85e7 Regenerate verilog 2020-06-17 13:02:20 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
Peter Rugg
49a9e5fc64 Remove unconnected signal in simulation 2020-06-17 11:43:28 +01:00
Peter Rugg
0e7df46dce Allow read/write of dpc 2020-06-17 11:42:58 +01:00
Peter Rugg
4f4bbbbdcb Add new TagController parameters to synth makefile 2020-06-17 11:40:23 +01:00
jon
dcfdb34f0a Changes to build with the now more parameterisable TagController. 2020-06-15 16:46:15 +01:00
jon
ad66967916 Bump capability library to version with fixed mask calculation. 2020-06-12 17:21:26 +01:00
jon
d35cea017e Bump to version allowing multiple outstanding requests. 2020-06-12 17:19:46 +01:00
jon
e08e97c17b Use the 80000000 entry point for RVFI_DII. 2020-06-11 15:59:19 +01:00
jon
6719925b78 Fetch initial instructions from boot rom in simulation to improve 
testing.
To make this not fail, remove the reset server behaviour in SoC_Top
which appears to not be needed as it is only calling reset servers upon
actual reset when everything has been reset anyway.
I suppose these reset servers are meant for debug-unit-initiated reset
events.
 2020-06-11 10:56:07 +01:00
jon
1de6fc941e Adjust debug output to always print certain portions as this is more 
useful.
 2020-06-11 09:47:19 +01:00
jon
c96021e5f2 Just fall through to default when the upper bits are not as expected to 
avoid lockup, though it may lockup anyway.  We should respond with a bus
error or something instead.
 2020-06-11 09:45:38 +01:00
jon
f582d6550b Add BLUESIM to two simulation builds as the TagController expects this 
variable to be set when building for simulation.
 2020-06-11 09:43:38 +01:00
jon
8492136abd Attempt to convert more functions in the MMIO platform to respect the 
alignment of the original data.
Also eliminate the call to the reimplementation of the AMO functions.
(One call was already converted to use the common function, and I've now
converted the other.)
It's honestly unknown how much of this works, but it's more likely to
work than what was previously implemented, I think, given that the
previou implementation was based on some basic misconceptions concerning
data alignment.
 2020-06-09 17:39:36 +01:00
jon
4b3f97cb6a More correct version of select function. 
Also the beginnings of a select function for writes which is not yet
used.
 2020-06-09 12:33:43 +01:00
jon
122e98b0c7 Attempt to provide correct alignment for MMIO requests in flits returned 
to bus.
This does not yet attempt to fix writes which might likely also need
fixing.
 2020-06-08 19:03:12 +01:00
Peter Rugg
3117fcc9d5 Regenerate verilog 2020-06-07 16:52:34 +01:00
Peter Rugg
4fbabae1dd component.xml fixes for synthesis 2020-06-07 16:52:29 +01:00
jon
9ec9b34376 Don't overwrite earlier exception in Execute. 2020-06-06 09:42:11 +01:00
jon
0fa18c6b1f Bump TagController to version that builds. 2020-06-06 09:40:48 +01:00
jon
afe61b0626 Bump tagcontroller to version which implements/optimises burst writes. 2020-06-05 19:34:13 +01:00
Peter Rugg
be2c92b291 Regenerate verilog 2020-06-05 17:49:32 +01:00
Jessica Clarke
e579f895dc CPU_Decode_C.bsv: Sync from Flute 
This incorporates the fix made to Piccolo and Flute to not trap on
C.FLWSP/C.FLDSP when rd == 0; unlike the compressed stack pointer
relative integer loads/stores, these are legal, since f0 is a real FPR
rather than a constant zero.
 2020-06-05 17:43:26 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00