Commit Graph

24 Commits

Author SHA1 Message Date
Alexandre Joannou
1a3915d8a2 Fix display message when running the dependency script 2020-04-27 15:27:16 +01:00
Alexandre Joannou
dfde021eb6 Avoid creation of outputfile on failure of dependency script + add beri license header 2020-04-24 15:09:04 +01:00
Alexandre Joannou
370ed61bc4 Integrate the generation of dependenices to Makefiles 2020-04-23 14:55:28 +01:00
jon
92e3216c69 Don't use special recursive build for the top level, as this just rebuilds everything. 2020-04-23 10:42:45 +01:00
Alexandre Joannou
aa79240629 generalise genDependencies a bit with env variables (no obvious getoptsin tcl AFAIK) 2020-04-23 02:04:19 +01:00
jon
f6b7132d4f Makefile updates to do a parallel build, including the tcl script to generate a dependency graph using the Bluespec compiler (which was written by Alexandre). 2020-04-22 22:44:19 +01:00
Jessica Clarke
a2aee1969d verilator_config.vlt: Revert "fix"
lint_off -rule is a very new feature that requires Verilator v4.026
released in Jan 2020, and is thus not in Ubuntu 18.04. Any breakage with
newer versions should be fixed in some other backwards-compatible way.
2020-04-16 17:12:27 +01:00
Alexandre Joannou
b5b2b4fe5c Port AXI4 changes from Flute 2020-03-27 16:45:26 +00:00
Alexandre Joannou
92815e957e Add BlueStuff to Makefile 2020-03-27 16:45:24 +00:00
Jonathan Woodruff
d77c158b76 Merge branch 'mac_build' into RVFI_DII 2020-03-20 11:35:11 +00:00
Jonathan Woodruff
b830f4bf41 Resolve some issues to build on mac.
This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
2020-03-19 19:21:59 +00:00
Jonathan Woodruff
3a79b022ea Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage! 2020-03-18 11:35:59 +00:00
Jonathan Woodruff
a7a2854888 Declarations required for updated socket library. 2020-03-12 10:45:34 +00:00
rsnikhil
96a0897bf5 In MMIO_AXI4_Adapter.bsv, added check for unmapped addresses, provide err response immediately.
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response.  Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
2020-02-28 14:07:45 -05:00
rsnikhil
83829590dd Fixed up logic for "Non-Debug-Module reset" request/response from the Debug Module
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
 - dm_reset, hart_reset, ndm_reset
 - break    (set breakpoint)
 - step
 - continue (until breakpoint of 'halt' command)
 - halt
 - read/write GPR, FPR, CSR, memory
 - elf_load
2020-02-04 16:02:53 -05:00
rsnikhil
0f04b9cbe1 Tweaks to builds/Resources/Include_..._.mk 2020-01-08 19:49:49 -05:00
James Clarke
7ecde58b1d Add RV64ACDFIMSU_Toooba_bluesim build 2020-01-04 22:44:59 +00:00
Jonathan Woodruff
909423e8e8 Use smaller L2 size (256KiB) for TestRIG. 2019-12-13 13:00:52 +00:00
Jonathan Woodruff
96d092c300 Changes that enable RVFI_DII to run.
It doesn't yet pass any set of tests, but tests do run and reduce.
2019-11-26 10:46:56 +00:00
Niraj Nayan Sharma
601bbe5a82 No longer using Xilinx FPU modules 2019-12-14 12:44:02 +05:30
rsnikhil
666dd2ad92 Small tweak to remove unnecessary explicit boot rom addrs (subsumed by IO) 2019-04-22 15:12:30 -04:00
rsnikhil
51bdff05d8 Updated Run_regression.py to utilize parallel processes 2019-04-18 18:42:06 -04:00
rsnikhil
47985fa93f Updated Makefiles so in src_SSITH_P3, RTL refers to Xilinx FP RTL instead of simulation models 2019-04-04 13:10:45 -04:00
rsnikhil
ee24a93944 Initial load of files 2019-03-26 14:49:40 -04:00