Peter Rugg
69b96cc68f
Extend the final missed id width
2023-02-10 17:09:20 +00:00
Peter Rugg
b0316afcb7
Extend missed id field width
2023-02-10 17:01:32 +00:00
Jonathan Woodruff
d9e842b785
Extend ID field to match current design.
...
This is likely to be cause of lockup in hardware.
2023-01-31 11:21:37 +00:00
Alexandre Joannou
95f554dad1
removed coreW from component.xml
2022-08-16 12:44:00 +00:00
Jonathan Woodruff
6ea972931d
Add missing verilog file that is inadvertantly used.
2022-02-23 16:46:43 +00:00
Peter Rugg
ac89600601
Add missing TSO dummy store buffer to component.xml
2021-04-23 16:33:26 +01:00
Jonathan Woodruff
db08e96596
Add Btb to the component.xml.
2021-03-03 20:27:31 +00:00
Peter Rugg
53eb073fb2
Don't track generated Verilog
2021-02-19 19:45:00 +00:00
jon
1fbf786294
Add to synthesis file set.
2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7
Add one more missing file and clean up some duplicates.
2021-02-17 18:37:52 +00:00
jon
5ba685b541
Try harder to remove all copies of references to old files.
2021-02-17 16:57:01 +00:00
jon
7a59cad288
Remove more no-longer-generated files from component.xml
2021-02-17 15:54:27 +00:00
jon
059f189bba
Attempt to add all current source files to componenet.xml.
2021-02-17 14:35:49 +00:00
Jessica Clarke
fb5339e9ca
Adapt the PLIC instantiation and wiring to support multiple cores
2021-01-31 17:54:43 +00:00
Jessica Clarke
6c98dcb3d8
src_SSITH_P3: Delete stray file references
...
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
2021-01-13 00:59:46 +00:00
Jonathan Woodruff
69c697daf7
Changes needed to build for FPGA.
2020-11-06 11:44:33 +00:00
Peter Rugg
8778369fe5
Merge remote-tracking branch 'upstream/master' into CHERI
2020-06-17 13:01:41 +01:00
Peter Rugg
4fbabae1dd
component.xml fixes for synthesis
2020-06-07 16:52:29 +01:00
Peter Rugg
962ade1092
Fixes for synthesis
2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909
Remove Tandem verification
2020-06-03 22:28:31 +01:00
rsnikhil
a6a227ed66
Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
...
Amendment: RegUNInit.v updated, removing an extraneous RST line.
2020-03-13 16:38:54 -04:00
Darius Rad
4fba332f17
Add missing module (FIFOL1) to Xilinx import.
2019-04-24 21:34:52 -04:00
Darius Rad
9b94fc9f58
Add files for GFE integration.
2019-04-09 14:08:36 -04:00
rsnikhil
113f888d37
Added support for 'debug_external_interrupt_req'
...
New method 'debug_external_interrupt_req' to support emulation of a
debug module starts at P3_Core interface and is plumbed all the way in
to the CSR register MIP as interrupt [14]. The corresponding MIE[14]
is always 1, so it is never masked. Still todo: should not be masked
by MSTATUS interrupt-enables either. Also expanded
interrupt-detection logic, mcause etc. to extend up to interrupt 14.
Builds in standalone mode, runs ISA tests.
Builds in src_SSITH_P3, generating RTL.
2019-04-01 12:26:54 -04:00
