Cheri-research/Toooba
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9baadf58f33269fe63b860f01544cc9a41e40321
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511 Commits

Author SHA1 Message Date
Jonathan Woodruff
9baadf58f3 Tune the size of the fetch pipeline fifos. This appears to make a 3% 
performance improvement in CoreMark.
 2024-01-26 16:02:18 +00:00
Jonathan Woodruff
e873bbd553 Clean up Fetch stage optimisations. This includes removing references 
to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged
(Fetch3 is now Fetch2).
 2024-01-26 15:14:03 +00:00
Jonathan Woodruff
ca4e120a6c Use DReg instead of Reg, as intended. 2024-01-22 12:06:39 +00:00
Jonathan Woodruff
b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is 
going ahead.
 2024-01-22 11:38:52 +00:00
Jonathan Woodruff
640f330d7d Briefly report flush when vm_info has a change in the itlb to give an 
opportunity to flush the buffered translations.
 2024-01-19 11:48:04 +00:00
Jonathan Woodruff
d30bd71e72 Allow consuming TLB response while TLB is being flushed. 2024-01-18 13:04:21 +00:00
Jonathan Woodruff
83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. 2024-01-17 16:09:42 +00:00
Jonathan Woodruff
9d12fefda8 Remove commented-out code. 2024-01-17 14:30:34 +00:00
Jonathan Woodruff
829a787be5 Move to vector functions as it's cleaner. 2024-01-17 13:41:43 +00:00
Jonathan Woodruff
5a1ed7c57f Allow a vector of translations to be remembered. 
Just do 2 for now.
 2024-01-17 13:21:38 +00:00
Jonathan Woodruff
4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the 
proper TLB lookup if necessary.
 2024-01-16 17:00:10 +00:00
Jonathan Woodruff
eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. 2024-01-16 10:05:17 +00:00
Jonathan Woodruff
25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
 2024-01-16 09:50:35 +00:00
Jonathan Woodruff
f9bf4ad856 Use default value on reset of Map. 2024-01-15 17:00:00 +00:00
Jonathan Woodruff
2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. 2024-01-09 17:12:39 +00:00
Jonathan Woodruff
2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to 
doRegReadMem.
 2024-01-09 12:37:34 +00:00
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
4acbe2f43b Fix build error with SPEC contracts 2023-07-17 17:38:57 +01:00
Peter Rugg
373b849d29 Merge branch 'tag-clear' into CHERI 2023-06-27 11:38:42 +01:00
Peter Rugg
ec4eacac9c Fix CSetAddr tag clear bug 2023-06-26 18:01:56 +01:00
Peter Rugg
86782f9bb5 Cleanup unused exception code 2023-06-20 16:46:39 +01:00
Peter Rugg
c8b0e12f79 Remove traps for CBuildCap 
This will be very expensive in terms of area and possibly timing.
Ideally this instruction would be multi-cycle or optimised to reduce the overhead.
 2023-06-20 16:23:44 +01:00
Peter Rugg
f3ac024b73 Remove exceptions from CUnseal 2023-06-20 12:32:49 +01:00
Peter Rugg
ca711eab2a Remove exceptions from CToPtr and CFromPtr 2023-06-20 09:45:48 +01:00
gameboo
e6a8111a1b Fix forgotten type change from tuple2 to tuple3 in mem exe pipeline 2023-06-14 11:49:09 +01:00
Jonathan Woodruff
f476990c65 Merge branch 'CHERI' into ks980-prefetch 2023-05-17 15:32:40 +00:00
Karlis Susters
5733ed9ac0 Implemented overflow bypass fifo, required for double target table 2023-04-12 21:58:35 +03:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Peter Rugg
2047a85b27 Fixes for the simplified debug unit DMA port 2023-02-28 14:55:20 +00:00
Jonathan Woodruff
f255193841 Vastly simplified DMA Connect that does not buffer data at all. 
This has not been tested yet, but it builds.
 2023-02-28 13:28:29 +00:00
Jonathan Woodruff
a91f15d10c Merge branch 'CHERI' into jdw57-512axi 2023-02-21 12:18:02 +00:00
Peter Rugg
e981b7625f Ban illegal JALR and Br encodings 2023-02-16 16:41:39 +00:00
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Peter Rugg
8ea0e07ce5 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-02-10 18:12:08 +00:00
Peter Rugg
6931201a14 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-01-31 21:02:17 +00:00
Peter Rugg
9f24a516e6 Remove traps from CSeal and CCSeal 2023-01-16 10:43:32 +00:00
Peter Rugg
ecdc2e0107 Remove remaining unsealed checks 2023-01-11 17:50:37 +00:00
Peter Rugg
4c166c95b9 Change treatment of reserved types in CCopyType 2023-01-11 17:40:51 +00:00
Alexandre Joannou
98e15acb3d Bump BlueStuff + use _Periph versions of parameters where needed 2022-11-18 12:07:24 +00:00
Jonathan Woodruff
4af4b647b1 Merge branch 'CHERI' into jdw57-512axi 2022-11-14 14:51:54 +00:00
Peter Rugg
e120b3427d Merge branch 'LoadTagsImprove' into CHERI 2022-11-14 13:28:44 +00:00
Jonathan Woodruff
ddf4afaf71 Changes to build with a 512-bit main data bus (with all other busses 
still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
 2022-11-11 17:52:32 +00:00
Peter Rugg
de0c0315f4 Remove trap conditions for CCopyType 2022-10-25 22:11:58 +01:00
Peter Rugg
b0233a01c4 Remove trap on CSetBounds* 2022-10-25 22:03:31 +01:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Peter Rugg
2b471b0196 Don't require permit_x when constructing sentries 2022-10-18 15:51:52 +01:00