This is not thoroughly tested, as we quickly throw an exception due to out-of-bounds memory and need some RVFI-DII control flow fixup to proceed further.
Otherwise, if the last instruction we tried to decode was the first half
of a 32-bit instruction, we will think the first 16-bit parcel from the
new PC is the second half of the previous instruction and take an
assertion failure because the PC does not match what was expected. This
fixes rv64uc-p-rvc, which broke after the previous commit as the
scheduling changes exposed this bug.
This conflict was introduced by 53aacff7c when compressed support was
added. Previously, doDecode could be scheduled in the same cycle as
doFetch3 (and only in that order), but the Reg reads added to doDecode
prevented this. Instead, use EHRs to allow a bypass path from doDecode
to doFetch3. This means we can issue every cycle again, rather than only
every other cycle.
This stopped unmapped addresses from faulting, instead giving back a
list of all Invalid entries, triggering the "Fetched insts not enough"
assertion in FetchStage's doDecode. Fixes rv64mi-p-access.
Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response. This was causing a deadlock.
Regression status: RV64ACDFIMSU_Toooba_verilator 207/229 PASS
This is in simulation only. The 22 failures are known and
expected; they are all in the floating-point tests, and are likely
due to the current inaccurate simulation-only models of
floating-point arithmetic.
When synthesized to FPGA, floating-point arithmetic is instead
done with vendor-supplied IP, and all tests are expected to pass.
Modified:
src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
In rule doPageWalk, if (!leafPte) ... else: added check for PPN alignment.
(In mega-/giga-page PTEs, lower bits of PPN must be zero for alignment)
Modified:
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
Bug fixes in 'getTrap' function:
- Trap if Fpu regs are accessed but mstatus_fs is "Off" (2'b00)
- Trap if r/w or privilege denies access to CSR in CSRRW/C/S instruction
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
Bug fix: add support for 'u' bit in function 'getExtensionBits'
Regression status: RV64ADFIMSU_Toooba_verilator 204/229 PASS
(22 expected floating-point failures due to inaccurate modeling)
Modified
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
Renamed 'BootRom' to 'IODevice'
Imported and instantiated SoC_Map
changed method getFetchTarget to use soc_map.is_IO_addr (phyPC)
to classify as IODevice
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Changed 'BootRom' constant to 'IODevice' constant (just a renaming)
src_Testbench/SoC/SoC_Map.bsv
Changed boot rom classification from 'mem' to 'IO device'
Modified
src_Core/CPU/MMIO_AXI4_Adapter.bsv
Instead of aborting on axi4 mem read error, pass the error on to the core
src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
Added mainMemBoundAddr
src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv
Update isMMIOAddr check to also check mainMemBoundAddr
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
Update getFetchTarget to also check mainMemBoundAddr
(still TODO: allow other IO addrs other than bootRom)
Modified:
src_Core/CPU/CsrFile.bsv
Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
for InstAccessFault and InstPageFault
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
for InstAccessFault and InstPageFault
LICENSE
README.md
Clarified licensing of MIT code and Bluespec code
Tests/Run_regression.py
Emptied out 'exclude_list'
builds/RV64ADFIMSU_Toooba_verilator/Makefile
Added 'C' to Makefile
Issue halt if haltreq is asserted and the hart is running. This
will ensure that the hart is always halted after ndmreset, as is
done with OpenOCD.
This corresponds to Flute commit 71d7e715f.
