Cheri-research/Toooba
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49e384ab2e6ed82d9631443fef4ece975def7738
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217 Commits

Author SHA1 Message Date
jon
49e384ab2e Don't wedge when peripherals return write errors. 2020-06-25 14:58:51 +01:00
jon
af6e562c84 Deq the incoming request when sending a fast error response to a bad mapping. 2020-06-25 14:20:28 +01:00
jon
86e143a9f7 Changes that are much more likely to work for uncached memory accesses, 
up to 128-bits.  I'm getting a lockup in simulation that I haven't
resolved yet, but the request looks ok.
 2020-06-24 19:45:34 +01:00
jon
312d0316da Use updated Bluestuff library, and also support uncached 128-bit transactions through MMIO. 2020-06-24 11:57:43 +01:00
jon
a51ddf17be Use the request ID in the response to the DMA interface. 2020-06-20 12:15:49 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
Peter Rugg
0e7df46dce Allow read/write of dpc 2020-06-17 11:42:58 +01:00
jon
dcfdb34f0a Changes to build with the now more parameterisable TagController. 2020-06-15 16:46:15 +01:00
jon
1de6fc941e Adjust debug output to always print certain portions as this is more 
useful.
 2020-06-11 09:47:19 +01:00
jon
c96021e5f2 Just fall through to default when the upper bits are not as expected to 
avoid lockup, though it may lockup anyway.  We should respond with a bus
error or something instead.
 2020-06-11 09:45:38 +01:00
jon
8492136abd Attempt to convert more functions in the MMIO platform to respect the 
alignment of the original data.
Also eliminate the call to the reimplementation of the AMO functions.
(One call was already converted to use the common function, and I've now
converted the other.)
It's honestly unknown how much of this works, but it's more likely to
work than what was previously implemented, I think, given that the
previou implementation was based on some basic misconceptions concerning
data alignment.
 2020-06-09 17:39:36 +01:00
jon
4b3f97cb6a More correct version of select function. 
Also the beginnings of a select function for writes which is not yet
used.
 2020-06-09 12:33:43 +01:00
jon
122e98b0c7 Attempt to provide correct alignment for MMIO requests in flits returned 
to bus.
This does not yet attempt to fix writes which might likely also need
fixing.
 2020-06-08 19:03:12 +01:00
jon
9ec9b34376 Don't overwrite earlier exception in Execute. 2020-06-06 09:42:11 +01:00
Jessica Clarke
e579f895dc CPU_Decode_C.bsv: Sync from Flute 
This incorporates the fix made to Piccolo and Flute to not trap on
C.FLWSP/C.FLDSP when rd == 0; unlike the compressed stack pointer
relative integer loads/stores, these are legal, since f0 is a real FPR
rather than a constant zero.
 2020-06-05 17:43:26 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Jessica Clarke
1d12a97741 CPU_Decode_C.bsv: Sync from Flute 
This incorporates the fix made to Piccolo and Flute to not trap on
C.FLWSP/C.FLDSP when rd == 0; unlike the compressed stack pointer
relative integer loads/stores, these are legal, since f0 is a real FPR
rather than a constant zero.
 2020-06-03 18:14:58 +01:00
Peter Rugg
9aeb8f1ea9 Fix CSR read immediate case 2020-06-02 20:50:56 +01:00
jon
7612738ff5 Changes needed for working TagController in Toooba. 2020-06-02 19:05:56 +01:00
jon
bb3eddccf2 Implement cap_mode switch for legacy loads and stores, as the mechanism 
for decoding has changed and was not setting the new flag.
 2020-06-02 19:00:28 +01:00
jon
078d39b9df Enable write bursts in LLC AXI4 adapter. 2020-06-02 09:40:37 +01:00
Peter Rugg
675de23dc2 Fix TestSubset top check the wrong way around 2020-06-01 20:23:42 +01:00
Peter Rugg
b7c73d4422 Link offset in JAL 2020-06-01 18:57:51 +01:00
Peter Rugg
1725cdda8f Fix bug where immediate discarded too early in Scr case 2020-06-01 15:12:30 +01:00
Peter Rugg
f7deb7349b Fix writeback when reading and writing CSR/SCR together 2020-06-01 15:04:59 +01:00
Peter Rugg
16eac986ef Fix EPC/MTVEC updates ignoring old value 2020-06-01 12:17:14 +01:00
Peter Rugg
6a8f0e5bc0 Rename 'cap-mode' in Mem pipeline to ddc offset, since explicit memory instructions contradicting the cap_mode exist 2020-05-29 17:05:03 +01:00
Peter Rugg
a7d4d8e4a4 Fix bug where explicit cap-rel mem accesses would always trap as untagged 2020-05-29 16:43:20 +01:00
Peter Rugg
4b4b5836e8 Populate tval with CHERI trap information 2020-05-29 13:27:23 +01:00
Peter Rugg
a49d3d2b6b Add ASR restrictions 2020-05-28 23:25:33 +01:00
jon
ffeed959a3 Believed-to-be-working attaching of tags to write bursts in the AXI4 LLC 
wrapper.
 2020-05-28 18:21:03 +01:00
jon
8ae5d3a1b2 Build RVFI_DII Toooba with very small caches, 2-way set associative to 
maximise cache and memory verification.
 2020-05-28 10:59:08 +01:00
Peter Rugg
57129f6383 Some minor cleanup of decode 2020-05-21 15:51:03 +01:00
Peter Rugg
2702f40b5e Initial implementation of CSetBoundsExact 2020-05-21 15:50:37 +01:00
Peter Rugg
791e862377 Initial (slow) implementation of CTestSubset 2020-05-21 15:49:25 +01:00
jon
0a84227f93 Implement DDC offset. 2020-05-20 18:03:14 +01:00
jon
d00ade6c9d Fix new-write-folding-in function to copy original tags where there are 
no byte-enables set.
 2020-05-20 13:31:09 +01:00
Peter Rugg
072c188f92 Initial implementation of CCSeal 2020-05-19 23:05:18 +01:00
Peter Rugg
61b97e090d Fix CFromPtr common case 2020-05-19 23:04:53 +01:00
Peter Rugg
e74220afc4 Implement CFromPtr 2020-05-19 02:37:53 +01:00
Peter Rugg
cd4d296a0c Initial attempt to allow reads/writes to xtvec, xepc via xtcc, xepcc 2020-05-14 17:22:39 +01:00
jon
82498cd963 Only unseal next_pc after exception checks have been made. 2020-05-13 12:48:23 +01:00
Peter Rugg
7c0dad18d6 Deal with separate kinds of sealing more explicitly 2020-05-13 12:02:03 +01:00
jon
a6fd7acf3e Temporary resolution of signExtension behaviour for getType. 
Peter intends to use getKind from an updated version of cheri-cap-lib.
 2020-05-12 17:25:44 +01:00
jon
0f0d1a983b Remove references to ScrFile which were mysteriously still here. 2020-05-12 17:24:50 +01:00
Peter Rugg
c65e89f6c1 Also enforce privilege checks for SCR reads 2020-05-12 13:28:40 +01:00
jon
854151978e Fix byte-enable merging tag logic in the cache (with help from 
Alexandre).
Also adjust priority in CCall exceptions.
 2020-05-12 12:25:45 +01:00
Peter Rugg
26919154db Merge branch 'pdr32-wip' into CHERI 2020-05-12 00:19:36 +01:00
Peter Rugg
8f4c6fbcce Decode CSpecialRW 0 as AUIPCC 2020-05-11 23:52:43 +01:00
Peter Rugg
f0bcd2ccd1 Don't write on CSpecialRW from R0 2020-05-11 23:52:04 +01:00