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Author SHA1 Message Date
Peter Rugg
7db3fa539f Add ALU bounds check 2020-04-20 11:21:51 +01:00
Peter Rugg
1bb53e5e86 Merge branch 'CHERI' into pdr32-wip 2020-04-16 20:58:37 +01:00
Peter Rugg
f1e04486b7 Work on SCR-related instructions 2020-04-16 20:53:08 +01:00
Peter Rugg
34c4e0f2fa Comment out user exception delegation SCRs since the corresponding CSRs are not yet supported 2020-04-16 20:43:44 +01:00
Peter Rugg
8269a0625e Initial implementation of set bounds 2020-04-16 20:39:54 +01:00
jon
4b2c3b1114 An attempt at doing the "right thing" with Jr targets and links with respect to PCC. 
This is not easy to test until we have CSetBounds.
 2020-04-16 18:07:39 +01:00
jon
a77ecc59af Checkpoint work to propagate register numbers into the exception code. 
There's another half of this left to do to propagate all the way into the CSR file.
 2020-04-16 17:28:28 +01:00
Jessica Clarke
3add2cac5e Move MakeReset0.v to src_bsc_lib_RTL like Piccolo and Flute 
This ensures it's shared across all simulator builds.
 2020-04-16 17:19:16 +01:00
Jessica Clarke
a2aee1969d verilator_config.vlt: Revert "fix" 
lint_off -rule is a very new feature that requires Verilator v4.026
released in Jan 2020, and is thus not in Ubuntu 18.04. Any breakage with
newer versions should be fixed in some other backwards-compatible way.
 2020-04-16 17:12:27 +01:00
jon
9bb3e835ac Fix operand of CCall. 
Also fix one case of CCopyType where it is meant to return nullWithAddr(-1).
 2020-04-16 11:38:38 +01:00
jon
c056d40a3a Trace the register that has been decoded rather than picking out the bits from the instruction. 
Duh.
 2020-04-15 14:08:36 +01:00
Peter Rugg
a0fb527ad7 Raise illegalInstruction for currently unsupported exceptions 2020-04-15 14:07:36 +01:00
Peter Rugg
e773cb0232 Add CIncOffsetImm 2020-04-15 14:06:46 +01:00
jon
9685bf1931 Implement CCall, hopefully as well as CJALR. 
This passes the unmodified TestRIG routine for CHERI Control Flow, which is very promising indeed!
There are some cases that are not covered there, but a lot is covered.
 2020-04-14 18:10:53 +01:00
Peter Rugg
72dc8f8bad Fix cap instructions not being sent to ALU 2020-04-07 19:55:09 +01:00
jon
56885f06c0 Changes for CJALR-only TestRIG to work. 
This includes replacing register read values with nullCap if reading x0, which is generally necessary.
This is more-or-less using a new mechanism which shouldn't actually be necessary if the default value in the register file is nullCap.
(In RVFI_DII, we initialise with the almightyCap instead.)
 2020-04-07 16:32:31 +01:00
Peter Rugg
ae78cd3d6a Don't track built files 2020-04-07 13:56:34 +01:00
Alexandre Joannou
198ce853bf Bump BlueStuff, cheri-cap-lib and BSV-RVFI-DII submodules 2020-04-07 12:48:37 +01:00
jon
beaf771e13 Bump subrepo. 2020-04-07 12:39:00 +01:00
jon
2918854bbc Add missing ifdef. 2020-04-07 12:37:14 +01:00
jon
850e632140 Changes for CJALR to work in a basic case, as well as piping CHERI exceptions through to commit, though the register isn't piped and I've undone some useful work for that piping. Oh well. 2020-04-06 18:18:05 +01:00
Peter Rugg
4ce8f54903 Add initial exception checks 2020-04-06 12:26:19 +01:00
jon
1ecdf73dd3 Make CJALR work like JALR but without an immediate. Seems to work! 
Obviously doesn't throw capability exceptions yet...
 2020-04-03 17:57:57 +01:00
jon
d07d6f4761 Add OpCHERI to the function that rationalises opcodes. 2020-04-03 16:42:14 +01:00
Peter Rugg
f20c644bae Add startings of decoding 2020-04-02 21:08:59 +01:00
jon
2c6ad40f93 Check the already decoded destination to decide to populate the register write data field in RVFI. 2020-04-02 17:10:52 +01:00
jon
b656f46859 Both enable tracing of floating-point register writes in RVFI-DII, and then properly not use them (since we're not expected to). 
This is better than using nonsense as we were previously doing on floating point instructions.
 2020-04-02 16:28:18 +01:00
jon
7618c5cec8 Trap on access of fcsr when floating point is not enabled. 2020-04-02 13:05:42 +01:00
jon
4714070aef Trace the next PC correctly for mret. 2020-04-01 18:43:48 +01:00
jon
c2917d558f Bump library version to that required by current design. 2020-04-01 14:44:21 +01:00
Peter Rugg
fe2420e42f Allow running isa_tests on CPUs with <=4 cores 2020-03-31 17:34:41 +01:00
Jonathan Woodruff
81da99237e Move the register file to CapReg format, and pipe CapPipe around the pipeline. 2020-03-31 15:44:23 +01:00
Jonathan Woodruff
0580a24b86 Bump library to version including new casts needed for recent changes. 2020-03-31 15:43:14 +01:00
Jonathan Woodruff
480b5923da Make type of register file generic. 2020-03-30 15:20:28 +01:00
Jonathan Woodruff
dbcc4a6c22 Re-add dummy Mem.hex file. 2020-03-30 15:18:01 +01:00
Jonathan Woodruff
db41e2b9ed An initial implementation of mccsr. 2020-03-27 17:47:02 +00:00
Alexandre Joannou
b5b2b4fe5c Port AXI4 changes from Flute 2020-03-27 16:45:26 +00:00
Alexandre Joannou
92815e957e Add BlueStuff to Makefile 2020-03-27 16:45:24 +00:00
Jonathan Woodruff
ded8dc72e7 Do the MTCC->PCC->MEPCC shuffle on trap. 2020-03-27 15:55:02 +00:00
Jonathan Woodruff
8d61c8db73 Remove unnecessary copy of submodule. 2020-03-27 15:54:06 +00:00
Jonathan Woodruff
c035f359e8 Merge branch 'CHERI' into pdr32-tmp 
and get it to build!
 2020-03-26 18:03:58 +00:00
Peter Rugg
5f33b1c87a Very initial decode and ALU work for CHERI 2020-03-26 14:35:02 +00:00
Jonathan Woodruff
d5b73a2d50 Add DDC exception. 
Also enable working exception reporting for the memory pipe.
 2020-03-26 14:29:06 +00:00
Jonathan Woodruff
f2f2285f75 Check the bounds on PCC and report the correct exception in Xcause registers. 
This required makeing the Exception type wider by one.
The actual "inBounds" check is currently implemented in the reorder buffer rows, which duplicates the logic ~80 times (number of outstanding instructions), which isn't ideal, but it's using the quick in-bounds check that only compares the mantissa-sized things.
 2020-03-25 15:20:03 +00:00
Jonathan Woodruff
88ca03f4ed Pipe through an exception to the Reorder buffer from each execute pipe. 
Also move to SetAddrUnsafe, as is traditional for setting the address of PCC where we do proper checks on branches so we really only have the possibility of executing off the end of the length, and therefore cannot become unrepresentable.
 2020-03-25 11:51:33 +00:00
Jonathan Woodruff
c813abe9c9 Write pcc bounds into reorderbuffer pc in the all execute pipeline stages. 
This allows pcc bounds to be consistent in the model of CSRs (written in commit and read in execute) in preparation for fancier forwarding eventually.
 2020-03-25 09:10:38 +00:00
Jonathan Woodruff
22938d2384 Propagate a CapPipe through the PC of each instruction record. 2020-03-23 17:24:05 +00:00
Jonathan Woodruff
2aa902f61a Change tabs to 8 spaces, this time being careful to do this only in BSV files. 2020-03-23 14:44:39 +00:00
Jonathan Woodruff
a6e5a7bff0 Revert "Fix whitespace in src_Core directory." 
This reverts commit a137a6ede7.
 2020-03-23 14:40:02 +00:00
Jonathan Woodruff
a137a6ede7 Fix whitespace in src_Core directory. 
Replace all tabs with 8 spaces.
 2020-03-23 14:28:00 +00:00