jon
9bbd8dc872
Bump the tag controller version to the one needed for Toooba.
2020-06-02 09:33:35 +01:00
Peter Rugg
675de23dc2
Fix TestSubset top check the wrong way around
2020-06-01 20:23:42 +01:00
Peter Rugg
b7c73d4422
Link offset in JAL
2020-06-01 18:57:51 +01:00
Peter Rugg
1725cdda8f
Fix bug where immediate discarded too early in Scr case
2020-06-01 15:12:30 +01:00
Peter Rugg
f7deb7349b
Fix writeback when reading and writing CSR/SCR together
2020-06-01 15:04:59 +01:00
Peter Rugg
16eac986ef
Fix EPC/MTVEC updates ignoring old value
2020-06-01 12:17:14 +01:00
Peter Rugg
6a8f0e5bc0
Rename 'cap-mode' in Mem pipeline to ddc offset, since explicit memory instructions contradicting the cap_mode exist
2020-05-29 17:05:03 +01:00
Peter Rugg
a7d4d8e4a4
Fix bug where explicit cap-rel mem accesses would always trap as untagged
2020-05-29 16:43:20 +01:00
Peter Rugg
4b4b5836e8
Populate tval with CHERI trap information
2020-05-29 13:27:23 +01:00
Peter Rugg
a49d3d2b6b
Add ASR restrictions
2020-05-28 23:25:33 +01:00
jon
ffeed959a3
Believed-to-be-working attaching of tags to write bursts in the AXI4 LLC
...
wrapper.
2020-05-28 18:21:03 +01:00
jon
8ae5d3a1b2
Build RVFI_DII Toooba with very small caches, 2-way set associative to
...
maximise cache and memory verification.
2020-05-28 10:59:08 +01:00
jon
8a07e18439
Do memory zeroing on reset when doing RVFI-DII.
...
I couldn't quite use the implementation from Flute as the register was
too wide for verilator.
This one uses wide memories instead, which is way complicated, but I
think it works. The width of the memory can be traded off for reset
speed. The width at the moment is 8192 bits, which seems to be fast
enough.
2020-05-28 10:55:46 +01:00
Peter Rugg
57129f6383
Some minor cleanup of decode
2020-05-21 15:51:03 +01:00
Peter Rugg
2702f40b5e
Initial implementation of CSetBoundsExact
2020-05-21 15:50:37 +01:00
Peter Rugg
791e862377
Initial (slow) implementation of CTestSubset
2020-05-21 15:49:25 +01:00
jon
0a84227f93
Implement DDC offset.
2020-05-20 18:03:14 +01:00
jon
d00ade6c9d
Fix new-write-folding-in function to copy original tags where there are
...
no byte-enables set.
2020-05-20 13:31:09 +01:00
Peter Rugg
072c188f92
Initial implementation of CCSeal
2020-05-19 23:05:18 +01:00
Peter Rugg
61b97e090d
Fix CFromPtr common case
2020-05-19 23:04:53 +01:00
Peter Rugg
372e4e4dfb
Bump BSV-RVFI-DII
2020-05-19 16:36:59 +01:00
Peter Rugg
e74220afc4
Implement CFromPtr
2020-05-19 02:37:53 +01:00
Peter Rugg
cd4d296a0c
Initial attempt to allow reads/writes to xtvec, xepc via xtcc, xepcc
2020-05-14 17:22:39 +01:00
jon
82498cd963
Only unseal next_pc after exception checks have been made.
2020-05-13 12:48:23 +01:00
Peter Rugg
7c0dad18d6
Deal with separate kinds of sealing more explicitly
2020-05-13 12:02:03 +01:00
jon
a6fd7acf3e
Temporary resolution of signExtension behaviour for getType.
...
Peter intends to use getKind from an updated version of cheri-cap-lib.
2020-05-12 17:25:44 +01:00
jon
0f0d1a983b
Remove references to ScrFile which were mysteriously still here.
2020-05-12 17:24:50 +01:00
Peter Rugg
c65e89f6c1
Also enforce privilege checks for SCR reads
2020-05-12 13:28:40 +01:00
jon
854151978e
Fix byte-enable merging tag logic in the cache (with help from
...
Alexandre).
Also adjust priority in CCall exceptions.
2020-05-12 12:25:45 +01:00
Peter Rugg
26919154db
Merge branch 'pdr32-wip' into CHERI
2020-05-12 00:19:36 +01:00
Peter Rugg
8f4c6fbcce
Decode CSpecialRW 0 as AUIPCC
2020-05-11 23:52:43 +01:00
Peter Rugg
f0bcd2ccd1
Don't write on CSpecialRW from R0
2020-05-11 23:52:04 +01:00
Peter Rugg
ec9f19dc26
Disable assert since normal instructions can read SCRs
2020-05-11 22:39:12 +01:00
Peter Rugg
20eb1129b1
Complete PCC checks
2020-05-11 17:25:21 +01:00
Peter Rugg
0ee9c65f3a
Forward cap-only instructions to the ALU
2020-05-11 17:24:43 +01:00
Peter Rugg
461ca6a703
Merge branch 'CHERI' into pdr32-wip
2020-05-11 14:08:42 +01:00
jon
6e00bd627b
Implement x0 default value in the memory pipe.
2020-05-11 12:21:57 +01:00
jon
cf39ec8368
Move to semantics suggested by Jess where we throw the exception on the
...
type of the code capability (src1, hopefully?) if the type is reserved.
2020-05-11 11:39:10 +01:00
jon
e3b532089d
Bounds-check the target of CCall.
...
Also handle more invalid decodings of explicit capability instructions
correctly.
2020-05-08 12:15:35 +01:00
jon
9631a9db4b
Rework exceptions in the memory pipeline to reconverge with the original
...
exception flow. This solves some issues with exceptions not being known
in some parts of the pipeline due to bypassing them.
2020-05-07 19:35:00 +01:00
Peter Rugg
f5ec436d19
Bump cheri-cap-lib
2020-05-07 16:34:09 +01:00
Peter Rugg
27947f4df7
Refactoring around SCRs
2020-05-07 16:19:26 +01:00
jon
77c7a6f3c0
Use the existing functions for casting.
2020-05-07 13:20:11 +01:00
jon
e3664c2bfd
Do sign extension properly on loads.
2020-05-07 12:17:14 +01:00
jon
9c0130a200
Support for permissions and bounds checks for memory operations, taking
...
the cap mode into account.
2020-05-06 18:48:44 +01:00
jon
cbb0d859c7
Feed capability checks and bounds checks into the memory pipe and back
...
into the reorder buffer.
2020-05-05 18:28:28 +01:00
jon
500811430b
Initial support for decoding Capability Memory instructions.
2020-05-05 12:23:10 +01:00
jon
21d1207e6b
The beginnings of an implementation of LQ and SQ.
...
Also a bug-fix to unseal nextPCC for control flow instructions, which
should only affect CCall (which was leaving PCC sealed).
2020-05-01 17:26:41 +01:00
jon
0177c2cd6e
Use the bounds of PCC to check legacy control flow instructions rather
...
than the bounds of the newPCC after C(Set/Inc)Offset, which may have
become unrepresentable.
2020-05-01 12:17:20 +01:00
jon
90d9d7cbc7
Move back to considering the instruction width when checking PCC.
2020-04-30 15:33:01 +01:00
