Cheri-research/Toooba
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aeae9b1f63b7ee325739817101d744a87b32e165
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712 Commits

Author SHA1 Message Date
Peter Rugg
aeae9b1f63 Busy the system bus when performing writes 
This was probably removed for performance, but now that we have
a faster workaround for loading kernels on the DE10, we should
probably prioritise accurate error information instead.
 2024-09-16 18:45:19 +01:00
Peter Rugg
af8432d3f3 Return Abstract Command Error on unsupported CSRs 2024-09-16 18:45:19 +01:00
gameboo
47e12b8e65 Revert "Use only 20 bits of address on the AXI lite port" 
This reverts commit c766187368.
 2024-09-11 20:02:35 +01:00
gameboo
c766187368 Use only 20 bits of address on the AXI lite port 2024-07-08 17:12:47 +01:00
Franz Fuchs
1f382b1563 Add license again to TourPred.bsv 2024-05-18 17:12:43 +01:00
Franz Fuchs
3532d44d56 Performed merge with CHERI 2024-04-16 16:42:37 +01:00
Franz Fuchs
598ac6574e Added working Konata support 
Konata: change M to F3

Added konata support to ALU pipeline

Added KONATA support to Fpu pipeline

Added KONATA support to Mem pipeline

Finished v1 of KONATA support

Added improvements to catch fragments in Konata

Kill fragments that have been merged

Fixed order of konata logs

Added commit stage output

Ensured that only the Commit stage can retire instructions in konata

Fixed printing commit stage log for Cap instructions

Changed Kanata to include the cycle counter for each line in the log file; please note that this requires post processing

Added reservation station support for Konata

Added parsing script for Toooba output

Removed double updated to D stage

Adressed Peter's comments
 2024-04-15 16:59:53 +01:00
Franz Fuchs
449070e347 Copied over preliminary Konata support from 89b0c37a7b 
The referenced commit did not merge well with our code base. Therefore, I copied over the changes manually. These changes do
not constitute a working Konata support for Toooba. In this commit, I commented out some things that did not compile, which will be fixed in future
 2024-04-15 16:57:20 +01:00
Jonathan Woodruff
6f8c371a5c Roll back DTlB to two cycles for timing on DE10. 2024-03-25 12:52:51 +00:00
Jonathan Woodruff
e0eefbcfd0 Be a little more careful with outstanding requests. 2024-03-18 09:10:55 +00:00
Jonathan Woodruff
271bc9c0e8 Experimentally remove deburster. 
This thing has a seraliser in it that serialises memory accesses, which
is a disaster for performance.
 2024-02-16 09:50:07 +00:00
Jonathan Woodruff
6838b02274 Move to 4-way L1 caches to reduce area usage of splitting data ways into 
seperate BRAMs.
 2024-02-05 09:40:15 +00:00
Jonathan Woodruff
0784902e45 Tune the instruction fetch FIFO to the lower-latency ICache. 2024-02-02 13:26:15 +00:00
Jonathan Woodruff
b65994c00c Include the new single-cycle CCPipe as a seperate implementation, and 
use it only in the L1 caches so that the L2 cache can have lower
resource utilisation and better timing.  (Resource utilisation is up
about 5% with the new design, and it's not necessary for the L2 cache.)
 2024-02-02 11:50:45 +00:00
Jonathan Woodruff
ccc71952bf Use forwarding BRAMs in L2 Cache. Duh; this is required for the new 
CCPipe structure.
 2024-02-01 13:44:36 +00:00
Jonathan Woodruff
7608543da5 Move back to more traditional implementation of the forwarded BRAM, 
which also workst.
 2024-02-01 10:07:48 +00:00
Jonathan Woodruff
3416040a74 Forward using a working forwarding memory rather than logic in CCPipe. 
This design runs CoreMark successfully.
 2024-01-31 13:29:59 +00:00
Jonathan Woodruff
0e87595d73 Work toward eliminating a cycle of cache latency by doing data lookup in 
parallel with tag lookup.
 2024-01-31 10:15:51 +00:00
Jonathan Woodruff
8e4848c4bc Turn off tracing in instruction fetch. 2024-01-26 16:32:16 +00:00
Jonathan Woodruff
be26ac9f79 Fix a typo in a comment. 2024-01-26 16:31:49 +00:00
Jonathan Woodruff
9baadf58f3 Tune the size of the fetch pipeline fifos. This appears to make a 3% 
performance improvement in CoreMark.
 2024-01-26 16:02:18 +00:00
Jonathan Woodruff
e873bbd553 Clean up Fetch stage optimisations. This includes removing references 
to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged
(Fetch3 is now Fetch2).
 2024-01-26 15:14:03 +00:00
Jonathan Woodruff
ca4e120a6c Use DReg instead of Reg, as intended. 2024-01-22 12:06:39 +00:00
Jonathan Woodruff
b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is 
going ahead.
 2024-01-22 11:38:52 +00:00
Jonathan Woodruff
640f330d7d Briefly report flush when vm_info has a change in the itlb to give an 
opportunity to flush the buffered translations.
 2024-01-19 11:48:04 +00:00
Jonathan Woodruff
d30bd71e72 Allow consuming TLB response while TLB is being flushed. 2024-01-18 13:04:21 +00:00
Jonathan Woodruff
83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. 2024-01-17 16:09:42 +00:00
Jonathan Woodruff
9d12fefda8 Remove commented-out code. 2024-01-17 14:30:34 +00:00
Jonathan Woodruff
829a787be5 Move to vector functions as it's cleaner. 2024-01-17 13:41:43 +00:00
Jonathan Woodruff
5a1ed7c57f Allow a vector of translations to be remembered. 
Just do 2 for now.
 2024-01-17 13:21:38 +00:00
Jonathan Woodruff
4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the 
proper TLB lookup if necessary.
 2024-01-16 17:00:10 +00:00
Jonathan Woodruff
eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. 2024-01-16 10:05:17 +00:00
Jonathan Woodruff
25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
 2024-01-16 09:50:35 +00:00
Jonathan Woodruff
f9bf4ad856 Use default value on reset of Map. 2024-01-15 17:00:00 +00:00
Jonathan Woodruff
2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. 2024-01-09 17:12:39 +00:00
Jonathan Woodruff
2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to 
doRegReadMem.
 2024-01-09 12:37:34 +00:00
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
4acbe2f43b Fix build error with SPEC contracts 2023-07-17 17:38:57 +01:00
gameboo
561683343d Add a mean to configure starting PC dynamically at start of simulation 2023-07-13 15:34:08 +01:00
Peter Rugg
373b849d29 Merge branch 'tag-clear' into CHERI 2023-06-27 11:38:42 +01:00
Peter Rugg
ec4eacac9c Fix CSetAddr tag clear bug 2023-06-26 18:01:56 +01:00
Jonathan Woodruff
3ebf537f71 Tidy up tracing options, including using RVFI when building for bluesim 
(which I'm sure we had meant to be doing?).
 2023-06-23 13:09:38 +00:00
Peter Rugg
86782f9bb5 Cleanup unused exception code 2023-06-20 16:46:39 +01:00
Peter Rugg
c8b0e12f79 Remove traps for CBuildCap 
This will be very expensive in terms of area and possibly timing.
Ideally this instruction would be multi-cycle or optimised to reduce the overhead.
 2023-06-20 16:23:44 +01:00
Peter Rugg
f3ac024b73 Remove exceptions from CUnseal 2023-06-20 12:32:49 +01:00
Peter Rugg
ca711eab2a Remove exceptions from CToPtr and CFromPtr 2023-06-20 09:45:48 +01:00
gameboo
e6a8111a1b Fix forgotten type change from tuple2 to tuple3 in mem exe pipeline 2023-06-14 11:49:09 +01:00