Cheri-research/Toooba
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e873bbd55376874f6ba9e09362f60f65f7e0fcc7
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574 Commits

Author SHA1 Message Date
Jonathan Woodruff
e873bbd553 Clean up Fetch stage optimisations. This includes removing references 
to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged
(Fetch3 is now Fetch2).
 2024-01-26 15:14:03 +00:00
Jonathan Woodruff
ca4e120a6c Use DReg instead of Reg, as intended. 2024-01-22 12:06:39 +00:00
Jonathan Woodruff
b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is 
going ahead.
 2024-01-22 11:38:52 +00:00
Jonathan Woodruff
640f330d7d Briefly report flush when vm_info has a change in the itlb to give an 
opportunity to flush the buffered translations.
 2024-01-19 11:48:04 +00:00
Jonathan Woodruff
d30bd71e72 Allow consuming TLB response while TLB is being flushed. 2024-01-18 13:04:21 +00:00
Jonathan Woodruff
83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. 2024-01-17 16:09:42 +00:00
Jonathan Woodruff
9d12fefda8 Remove commented-out code. 2024-01-17 14:30:34 +00:00
Jonathan Woodruff
829a787be5 Move to vector functions as it's cleaner. 2024-01-17 13:41:43 +00:00
Jonathan Woodruff
5a1ed7c57f Allow a vector of translations to be remembered. 
Just do 2 for now.
 2024-01-17 13:21:38 +00:00
Jonathan Woodruff
4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the 
proper TLB lookup if necessary.
 2024-01-16 17:00:10 +00:00
Jonathan Woodruff
eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. 2024-01-16 10:05:17 +00:00
Jonathan Woodruff
25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
 2024-01-16 09:50:35 +00:00
Jonathan Woodruff
f9bf4ad856 Use default value on reset of Map. 2024-01-15 17:00:00 +00:00
Jonathan Woodruff
2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. 2024-01-09 17:12:39 +00:00
Jonathan Woodruff
2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to 
doRegReadMem.
 2024-01-09 12:37:34 +00:00
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
4acbe2f43b Fix build error with SPEC contracts 2023-07-17 17:38:57 +01:00
Peter Rugg
373b849d29 Merge branch 'tag-clear' into CHERI 2023-06-27 11:38:42 +01:00
Peter Rugg
ec4eacac9c Fix CSetAddr tag clear bug 2023-06-26 18:01:56 +01:00
Jonathan Woodruff
3ebf537f71 Tidy up tracing options, including using RVFI when building for bluesim 
(which I'm sure we had meant to be doing?).
 2023-06-23 13:09:38 +00:00
Peter Rugg
86782f9bb5 Cleanup unused exception code 2023-06-20 16:46:39 +01:00
Peter Rugg
c8b0e12f79 Remove traps for CBuildCap 
This will be very expensive in terms of area and possibly timing.
Ideally this instruction would be multi-cycle or optimised to reduce the overhead.
 2023-06-20 16:23:44 +01:00
Peter Rugg
f3ac024b73 Remove exceptions from CUnseal 2023-06-20 12:32:49 +01:00
Peter Rugg
ca711eab2a Remove exceptions from CToPtr and CFromPtr 2023-06-20 09:45:48 +01:00
gameboo
e6a8111a1b Fix forgotten type change from tuple2 to tuple3 in mem exe pipeline 2023-06-14 11:49:09 +01:00
Jonathan Woodruff
410be14a25 Merge remote-tracking branch 'karlis/CHERI' into ks980-prefetch 2023-05-23 17:34:19 +00:00
Karlis Susters
373d92c17a Added license text 2023-05-23 13:37:43 +01:00
Karlis Susters
35524a2a50 Revert L1 store counters to tracking stores 2023-05-18 13:34:39 +01:00
Jonathan Woodruff
f476990c65 Merge branch 'CHERI' into ks980-prefetch 2023-05-17 15:32:40 +00:00
Karlis Susters
2ae2b99268 Move Prefetcher unit tests to unit test folder 2023-05-11 00:10:32 +01:00
Karlis Susters
3098b8afba Other code cleanup 2023-05-10 23:59:35 +01:00
Karlis Susters
1776ba3317 Prefetcher code cleanup 2023-05-10 23:55:05 +01:00
Karlis Susters
05e5ad5076 Update tests for singlewindow-target 2023-05-10 23:51:16 +01:00
Karlis Susters
0554fad990 Config for L1D MarkovDouble 2023-04-25 13:05:01 +01:00
Karlis Susters
88fee870d0 Minor update to single-window-target 2023-04-22 10:00:50 +01:00
Karlis Susters
3953581b50 Fix stride prefetcher mis-commit 2023-04-22 10:00:15 +01:00
Karlis Susters
754627d4e8 Stride: block prefetches out of page bounds, and reduce stride bit length 2023-04-21 16:05:10 +01:00
Karlis Susters
b5a3a78e58 Minor change to multi window prefetcher design 2023-04-20 17:05:59 +01:00
Karlis Susters
4bc04b581d Config for L1I MultiWindowTarget-2 2023-04-19 14:22:01 +03:00
Karlis Susters
cc65297cf9 simplified simple stride slightly 2023-04-15 15:49:34 +03:00
Karlis Susters
8e3d6409c0 Simplified Stride2 code, using Int type 2023-04-15 15:37:59 +03:00
Karlis Susters
2f428a974a Reduce bit storage for stride prefetcher 2023-04-13 18:27:28 +03:00
Karlis Susters
2ec0f37bbd Remove stride prefetcher empty state 2023-04-13 13:39:22 +03:00
Karlis Susters
0e4b9a710a Implemented SimpleStride, to compare with Gem5 2023-04-12 23:31:15 +03:00
Karlis Susters
5733ed9ac0 Implemented overflow bypass fifo, required for double target table 2023-04-12 21:58:35 +03:00
Karlis Susters
f20e80e5b2 Tests for prefetchervector, double target table, overflow bypass fifo 2023-04-12 21:57:03 +03:00
Karlis Susters
d2b41c852d Added prefetcher port to ICrqmshr and retired prefetchRqDone 2023-04-12 21:55:13 +03:00