Jessica Clarke
a8299cfc01
CCTypes: Fix misleading bit width for MESI/Msi enum
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4 does not fit in 2 bits. This appears to not matter in practice, as a
spot check of the generated Verilog shows 3'dN for state-related
constants, but we should not be relying on this surprisingly lax
behaviour from bsc, and who knows if there are ways in which bsc does
end up using the as-written bit width somewhere.
Fixes: 6d4644ce73
2025-11-02 14:28:02 +00:00
Jonathan Woodruff
e576a2cae7
Revert "Changes to make Prefetcher more deterministic, and also to report schedules."
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This reverts commit f964e1dd2c
2025-07-03 11:47:00 +01:00
Jonathan Woodruff
acbf07ddf0
Merge pull request #46 from CTSRD-CHERI/CHERI-benchmarks
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Cheri benchmarks
2025-06-12 10:15:45 +01:00
Yuecheng-CAM
8af3b2e85a
Revert "initial commit, test compiled and run sucessfully"
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This reverts commit d025278195
2025-06-01 18:17:24 +01:00
Yuecheng-CAM
d025278195
initial commit, test compiled and run sucessfully
2025-06-01 18:14:19 +01:00
Jonathan Woodruff
f964e1dd2c
Changes to make Prefetcher more deterministic, and also to report schedules.
2025-05-20 16:32:33 +01:00
Louis Hobson
769a6aec83
merge fix in L1Pipe
2025-03-25 09:23:08 +00:00
Louis Hobson
0c634fc019
Better print statements
2025-03-25 09:23:08 +00:00
Louis Hobson
a08a701805
Let cRqNum increase
2025-03-25 09:23:07 +00:00
Louis Hobson
c28c6c3670
Fix bad IBank merge
2025-03-25 09:23:07 +00:00
Louis Hobson
657e7e529b
Turn verbose on
2025-03-25 09:23:07 +00:00
Louis Hobson
535d85ff35
Request queues in L1 cache
2025-03-25 09:23:06 +00:00
Peter Rugg
1df304a820
Prevent various debug prints by default
2025-01-08 18:43:05 +00:00
Jonathan Woodruff
b65994c00c
Include the new single-cycle CCPipe as a seperate implementation, and
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use it only in the L1 caches so that the L2 cache can have lower
resource utilisation and better timing. (Resource utilisation is up
about 5% with the new design, and it's not necessary for the L2 cache.)
2024-02-02 11:50:45 +00:00
Jonathan Woodruff
ccc71952bf
Use forwarding BRAMs in L2 Cache. Duh; this is required for the new
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CCPipe structure.
2024-02-01 13:44:36 +00:00
Jonathan Woodruff
7608543da5
Move back to more traditional implementation of the forwarded BRAM,
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which also workst.
2024-02-01 10:07:48 +00:00
Jonathan Woodruff
3416040a74
Forward using a working forwarding memory rather than logic in CCPipe.
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This design runs CoreMark successfully.
2024-01-31 13:29:59 +00:00
Jonathan Woodruff
0e87595d73
Work toward eliminating a cycle of cache latency by doing data lookup in
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parallel with tag lookup.
2024-01-31 10:15:51 +00:00
Jonathan Woodruff
3ebf537f71
Tidy up tracing options, including using RVFI when building for bluesim
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(which I'm sure we had meant to be doing?).
2023-06-23 13:09:38 +00:00
Karlis Susters
373d92c17a
Added license text
2023-05-23 13:37:43 +01:00
Karlis Susters
35524a2a50
Revert L1 store counters to tracking stores
2023-05-18 13:34:39 +01:00
Karlis Susters
2ae2b99268
Move Prefetcher unit tests to unit test folder
2023-05-11 00:10:32 +01:00
Karlis Susters
3098b8afba
Other code cleanup
2023-05-10 23:59:35 +01:00
Karlis Susters
1776ba3317
Prefetcher code cleanup
2023-05-10 23:55:05 +01:00
Karlis Susters
05e5ad5076
Update tests for singlewindow-target
2023-05-10 23:51:16 +01:00
Karlis Susters
0554fad990
Config for L1D MarkovDouble
2023-04-25 13:05:01 +01:00
Karlis Susters
88fee870d0
Minor update to single-window-target
2023-04-22 10:00:50 +01:00
Karlis Susters
3953581b50
Fix stride prefetcher mis-commit
2023-04-22 10:00:15 +01:00
Karlis Susters
754627d4e8
Stride: block prefetches out of page bounds, and reduce stride bit length
2023-04-21 16:05:10 +01:00
Karlis Susters
b5a3a78e58
Minor change to multi window prefetcher design
2023-04-20 17:05:59 +01:00
Karlis Susters
4bc04b581d
Config for L1I MultiWindowTarget-2
2023-04-19 14:22:01 +03:00
Karlis Susters
cc65297cf9
simplified simple stride slightly
2023-04-15 15:49:34 +03:00
Karlis Susters
8e3d6409c0
Simplified Stride2 code, using Int type
2023-04-15 15:37:59 +03:00
Karlis Susters
2f428a974a
Reduce bit storage for stride prefetcher
2023-04-13 18:27:28 +03:00
Karlis Susters
2ec0f37bbd
Remove stride prefetcher empty state
2023-04-13 13:39:22 +03:00
Karlis Susters
0e4b9a710a
Implemented SimpleStride, to compare with Gem5
2023-04-12 23:31:15 +03:00
Karlis Susters
f20e80e5b2
Tests for prefetchervector, double target table, overflow bypass fifo
2023-04-12 21:57:03 +03:00
Karlis Susters
d2b41c852d
Added prefetcher port to ICrqmshr and retired prefetchRqDone
2023-04-12 21:55:13 +03:00
Karlis Susters
bf0f26ce56
Implemented double target table and the corresponding markov prefetcher
2023-04-12 21:52:56 +03:00
Karlis Susters
2d94cba951
Implemented vector prefetcher setup in L2
2023-04-12 21:50:31 +03:00
Karlis Susters
4ea9b17971
Minor changes to targettable and instruction target prefetchers
2023-04-12 21:31:08 +03:00
Karlis Susters
1ad1dfad6a
Config for MarkovOnHit-2-8KiB.
2023-03-30 13:07:34 +01:00
Karlis Susters
625dbb3066
Count sent prefetch requests as Store misses, cache full cycles as stores
2023-03-30 13:06:12 +01:00
Karlis Susters
06651f1a31
Actually repurpose L1D store count, not store miss count
2023-03-24 15:15:03 +00:00
Karlis Susters
7d7d38ad49
Repurpose L1D store miss count to track number of cycles cache is full
2023-03-24 15:11:08 +00:00
Karlis Susters
a4ad28d865
Config for MarkovOnHit-1-bigtable
2023-03-23 11:09:36 +00:00
Karlis Susters
643afd81e2
Implementation and config for L1D StrideV2-2 prefetcher
2023-03-22 22:12:59 +00:00
Karlis Susters
808d961a7b
Implementation and config for L1D MarkovOnHit-2-BigTable
2023-03-21 19:26:38 +00:00
Karlis Susters
1123f43423
Config for L1D Markov-2-Bigtable
2023-03-20 13:04:21 +00:00
Karlis Susters
e584786c93
Bugfix to Stride Adaptive config
2023-03-17 11:26:23 +00:00
