Cheri-research/Toooba
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Author SHA1 Message Date
Peter Rugg
1b5f4ee9e0 Add capability-aware compressed decoding 2021-05-26 16:25:55 +01:00
Peter Rugg
88751cccba Remove hardcoded field encodings for cap loads and stores 2021-05-26 16:25:55 +01:00
Peter Rugg
913d14406e Add explicit PCC and cap JALRs 2021-05-26 16:24:41 +01:00
Peter Rugg
6450d9c33c Make JAL and JALR mode-dependent 2021-05-26 16:24:41 +01:00
Peter Rugg
657124671c Support amoswap.c 2021-05-13 23:15:25 +01:00
Peter Rugg
abc70134b1 Don't take load cap page faults if the authorising cap doesn't have load cap 2021-05-13 23:15:25 +01:00
PeterRugg
f1ceaa4b3b Merge pull request #11 from CTSRD-CHERI/faf28_fix_hpm 
Fixed the implementation of mcountinhibit in CsrFile
 2021-05-12 13:41:12 +01:00
Franz Fuchs
d78a2799d3 Fixed small mistake pointed out by Peter(pdr32) 2021-05-12 10:46:07 +01:00
Franz Fuchs
fcea3a1f4e included suggestions from Peter (pdr32) 2021-05-11 19:28:49 +01:00
Franz Fuchs
f6bd0b0e1b first attempts to fix inhibit mismatch 2021-05-11 14:13:02 +01:00
jon
1620aae1de Bump Bluestuff. 2021-05-08 07:32:02 +01:00
Peter Rugg
0a7e77230e Style improvements (suggested by jrtc27) 2021-05-05 13:32:07 +01:00
Peter Rugg
7e77b2314b Clarify precedence in VM permission check 2021-05-05 13:32:07 +01:00
Peter Rugg
e7258f0f22 Plumb through info on whether a load is capWidth to the TLB 2021-05-05 13:32:07 +01:00
jon
b8d86df2d0 Guard Meltdown_CF protection (such as it is) with ifdef rather than just 
comment it out.
 2021-05-04 11:29:36 +01:00
jon
2dccf1b557 Add (not-enabled-by-defaul) Meltdown-CF fix which resolves CUnseal, but not any 
of the ones that require a bounds-check.
This isn't enabled by default so that we can evaluate the seriousness of
the vulnerabilities.
 2021-04-29 17:46:39 +01:00
Peter Rugg
48e22af43e Factor out PTE cap invalid check 2021-04-29 16:02:30 +01:00
Peter Rugg
005ba1bd6f Add LoadCapPageFault exception cases 2021-04-29 16:02:30 +01:00
Peter Rugg
1eef5d2979 Still advance the DII stream on instruction fetch PTE fault (with jrtc27) 2021-04-29 16:02:30 +01:00
Peter Rugg
3b07a2a17c Add revocation 3.0 bits 2021-04-29 16:02:30 +01:00
PeterRugg
eb46b59bdc Merge pull request #10 from nwf/202104-cappagefault-mtval 
Set mtval for excStoreCapPageFault-s correctly
 2021-04-26 08:48:14 +01:00
Nathaniel Filardo
55da2986af Set mtval for excStoreCapPageFault-s correctly 
These were previously defaulting to 0, deeply confusing the kernel.
 2021-04-26 02:07:10 +01:00
Peter Rugg
ac89600601 Add missing TSO dummy store buffer to component.xml 2021-04-23 16:33:26 +01:00
Peter Rugg
10b5cd7ad7 Switch to TSO 2021-04-22 18:22:02 +01:00
jon
9b88dc4ce0 Bump TagController to version with 128K, not 1M. 2021-04-22 10:35:18 +01:00
jon
702eab2ee4 Bump to latest version of TagController. 
We failed to bump in this repo for thet last size increase of the
TagCache, but there was also a misunderstanding about what size we were
getting.
This one moves from 64KiB 2-way to 128KiB 4-way.
 2021-04-21 12:26:19 +01:00
jon
7cefaacb86 Remove wayward disabling of consistency flush case for the weak memory 
model.
 2021-04-21 10:44:31 +01:00
Jonathan Woodruff
280ace318e Bump TagController to quadruple the size again. 2021-04-15 14:27:41 +00:00
jon
86afb7e68e Add counter for LL writebacks (in the ST_MISS field). 2021-04-12 16:21:58 +01:00
Peter Rugg
53549e0dbc Set number of cores using RISCY config instead of manual define 
This was leading to -D NUM_CORES=2 -D NUM_CORES=1 in the command.
The NUM_CORES=2 seems to have been winning, but this is obviously
far from ideal.
 2021-04-12 13:10:12 +01:00
jon
2c41fcd7fb Fix bug and improve expression by using Int. 2021-04-12 12:48:49 +01:00
jon
4776bc0a11 Double-train on killing a load (still decrement by one on success). 
This combo got the best performance overall (I tested triple and
quadruple training).
 2021-04-12 06:34:16 +01:00
jon
8e3fd534f9 Do negative training when we encounter a load that has previously been 
killed, but was not killed this time.
 2021-04-10 08:47:05 +01:00
jon
aa9e57ce10 Fix bug so that we actually start at minBound. 
(Map defaults to unpack(0), so for an Int, our first updateFunc will add
one to zero and it won't be much different than before.)
 2021-04-10 07:54:39 +01:00
jon
6b871c0442 Use a saturating add before being conservative with issuing loads. 2021-04-09 16:21:55 +01:00
Peter Rugg
fcea5365f6 Initial implementation CLoadTags 
This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
 2021-04-08 17:08:15 +01:00
jon
103835db72 Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-04-08 14:41:48 +01:00
jon
0be771df4c Bump TagController to one with 32KiB cache. 2021-04-08 14:40:49 +01:00
Peter Rugg
b232272ad1 Treat CCSeal with an out-of-bounds capability as a move 
See 2d7ae22c0a for corresponding Sail change

This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
 2021-04-08 13:08:46 +01:00
jon
12ac14c1ca Move to config registers here as this affects scheduling. 2021-04-07 17:47:49 +01:00
Marno van der Maas
3f059cbd94 Added note on bsc-contrib dependency to SSITH readme 2021-04-07 11:53:48 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Franz Fuchs
6e157fff5a Small improvement of BTB changes made by Jon and myself 2021-04-01 09:08:47 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
84271b2712 Changes to build (and run?) with TSO_MM. 2021-03-29 12:03:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00