Cheri-research/Toooba
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3e3531ffd52673260edb418dd4e2a0be9acca06e
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354 Commits

Author SHA1 Message Date
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
373b849d29 Merge branch 'tag-clear' into CHERI 2023-06-27 11:38:42 +01:00
Peter Rugg
ec4eacac9c Fix CSetAddr tag clear bug 2023-06-26 18:01:56 +01:00
Peter Rugg
86782f9bb5 Cleanup unused exception code 2023-06-20 16:46:39 +01:00
Peter Rugg
c8b0e12f79 Remove traps for CBuildCap 
This will be very expensive in terms of area and possibly timing.
Ideally this instruction would be multi-cycle or optimised to reduce the overhead.
 2023-06-20 16:23:44 +01:00
Peter Rugg
f3ac024b73 Remove exceptions from CUnseal 2023-06-20 12:32:49 +01:00
Peter Rugg
ca711eab2a Remove exceptions from CToPtr and CFromPtr 2023-06-20 09:45:48 +01:00
Jonathan Woodruff
f476990c65 Merge branch 'CHERI' into ks980-prefetch 2023-05-17 15:32:40 +00:00
Karlis Susters
5733ed9ac0 Implemented overflow bypass fifo, required for double target table 2023-04-12 21:58:35 +03:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Peter Rugg
2047a85b27 Fixes for the simplified debug unit DMA port 2023-02-28 14:55:20 +00:00
Jonathan Woodruff
f255193841 Vastly simplified DMA Connect that does not buffer data at all. 
This has not been tested yet, but it builds.
 2023-02-28 13:28:29 +00:00
Jonathan Woodruff
a91f15d10c Merge branch 'CHERI' into jdw57-512axi 2023-02-21 12:18:02 +00:00
Peter Rugg
e981b7625f Ban illegal JALR and Br encodings 2023-02-16 16:41:39 +00:00
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Peter Rugg
9f24a516e6 Remove traps from CSeal and CCSeal 2023-01-16 10:43:32 +00:00
Peter Rugg
ecdc2e0107 Remove remaining unsealed checks 2023-01-11 17:50:37 +00:00
Peter Rugg
4c166c95b9 Change treatment of reserved types in CCopyType 2023-01-11 17:40:51 +00:00
Alexandre Joannou
98e15acb3d Bump BlueStuff + use _Periph versions of parameters where needed 2022-11-18 12:07:24 +00:00
Jonathan Woodruff
ddf4afaf71 Changes to build with a 512-bit main data bus (with all other busses 
still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
 2022-11-11 17:52:32 +00:00
Peter Rugg
de0c0315f4 Remove trap conditions for CCopyType 2022-10-25 22:11:58 +01:00
Peter Rugg
b0233a01c4 Remove trap on CSetBounds* 2022-10-25 22:03:31 +01:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Peter Rugg
2b471b0196 Don't require permit_x when constructing sentries 2022-10-18 15:51:52 +01:00
Peter Rugg
04ba0cb7ab Prefer tag clearing to trapping when manipulating a sealed capability 
This causes the behaviour of CCSeal and CSeal to diverge in non-trapping cases,
meaning an extra case is added to CapModify.
 2022-10-18 15:48:35 +01:00
Jonathan Woodruff
1fceb8fa72 Use standard imports as the fixes have been upstreamed. 2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b NonPipelined API update 2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38 Use NonPipelined dividers + update "reset_by" in CoreW 2022-08-15 16:18:23 +00:00
Franz Fuchs
2f595167a4 commented out debug print statements in Ras.bsv 2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d added typedefs to STLPred 2022-07-26 09:18:20 +01:00
Franz Fuchs
4abf838d62 implemented missing notFull method in SpecFifo 2022-07-11 14:56:30 +01:00
Franz Fuchs
c85b13c5af added MELTDOWN_CF ifdef and enabled it 2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc Attempt to clear tag on exception path before forwarding. 
This is likely to be bad for timing, but might just work at 25MHz.
 2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a corrected ifdef in STLPred.bsv 2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093 added no prediction STL predictor 2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa added STL predictor module and moved state from SplitLSQ to it 2022-06-08 12:04:25 +01:00
Peter Rugg
e37339b147 Return 0 on CToPtr if authority tag unset 2022-05-18 14:59:56 +01:00
Peter Rugg
338b98e0d2 Remove tag-assertions when manipulating capabilities 2022-05-18 14:59:56 +01:00
Franz Fuchs
fd639f4b22 added typedef for static number in Ras.bsv 2022-05-14 17:16:40 +01:00
Jonathan Woodruff
9bfaf4cbf0 Swap poliarity of prediction for comparison with upstream. 2022-03-25 14:03:06 +00:00
Jonathan Woodruff
6d7f95571f Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction 2022-03-25 13:06:22 +00:00
Jonathan Woodruff
3cdc2d31c8 Experimentally increase delay before reset. 2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8 Reset counter if head becomes valid. 2022-03-16 11:39:57 +00:00
Jonathan Woodruff
7b78c0ed7b Delay returns (up to 10 cycles) if there is an outstanding push. 2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1 Clean up prints 2022-03-11 10:24:39 +00:00