Cheri-research/Toooba
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4cfd652b0d5eb3fa3a607e1307faaa5fca314aac
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275 Commits

Author SHA1 Message Date
Jonathan Woodruff
4cfd652b0d Use mkRegOR in register file. 2022-01-25 20:42:16 +00:00
Jonathan Woodruff
e497091e18 A timing optimisation for the direction predictor. 
Add a "nextPc" interface so that lookup can begin in the previous cycle.
Remove the "pc" operands in the vector of lookup interfaces,
but rather derive the PC from lookup from the first PC being looked up
in that cycle. That is, by adding 4*(interface number) to the beginning
lookup PC.  As this might not actually be the PC of the instruction,
pass the index you used with the training info so that you are certain
to train with the same index you looked up.

This has less than 1% overhead in CoreMark.

This is a general improvement for reasonable timing which should be upstreamed.
 2022-01-18 11:05:09 +00:00
Jonathan Woodruff
1f8181d595 Move to (recently merged) non-pipelined Divide. 2022-01-13 11:14:20 +00:00
Jonathan Woodruff
37f6dbde93 Timing optimisation for Tournament Predictor. 
Start global-history-indexed lookups in the previous cycle.
This is a general timing optimisation that should be pushed upstream at
some point.
 2022-01-12 16:08:33 +00:00
Jonathan Woodruff
e600fd7d38 Delay BTB update by a cycle for timing. 
This should not be a primary degredation of performance since the
redirection gets on seperately from this update which will only affect
future predictions.
 2022-01-08 10:16:50 +00:00
Jonathan Woodruff
b84562a027 Improve scheduling for LatencyTimer to improve timing path discovered on 
DE10.
 2022-01-07 09:52:43 +00:00
Jonathan Woodruff
f619f4b0a1 Make the associative BTB compressed. 
That is, only store the bottom 16 bits of the target if the upper bits
of pc and nextPc match.
Have a single "way" dedicated to full targets.
 2021-12-20 17:24:55 +00:00
Jonathan Woodruff
34c6ee1894 Specifically give priority to wrong_spec when they conflict. 
This appears to yield 10% performance improvement as our default setup
appears to choose a wrong priority.
 2021-12-03 12:36:40 +00:00
Franz Fuchs
37074525e1 removed unnecessary execute permissions for Decode.bsv, Exec.bsv, ProcTypes.bsv, ReorderBuffer.bsv, and AluExePipeline.bsv 2021-11-29 10:38:23 +00:00
Jonathan Woodruff
59836cc9e5 Hopefully optimise this function to have just one call to modifyOffset. 2021-11-26 11:07:12 +00:00
Marno
0f86f09b6a Updated copyright statement 2021-11-11 12:15:45 +00:00
Marno
6ae92f786b Checking tag and seal on rVal2 and checking type on rVal1 in a way that does not use undefined behavior. 2021-11-11 11:36:45 +00:00
Marno
4d1dc29f79 Added ccopytype_bypass 2021-11-10 11:53:26 +00:00
Jonathan Woodruff
d5e52a9ecb Revert to upstream direction predictors to reduce diffs and prepare for 
improvements that can be upstreamed.
Basically, only use addresses in these predictors rather than
capabilities, and just pass an address in from the FetchStage.
 2021-11-05 17:42:19 +00:00
Jonathan Woodruff
836ed5b143 Merge branch 'jdw57-jr-bsc-safety' into CHERI 2021-11-03 16:46:21 +00:00
Jonathan Woodruff
3908c5f955 A merge resolution not included in previous commit due to not saving file. 
Doh.
 2021-11-02 18:12:05 +00:00
Jonathan Woodruff
7437c0c5e7 Some cleanups. 2021-11-02 18:09:06 +00:00
Jessica Clarke
fb1a629e07 Decode: Fix capability width mode-dependent LR/SC 
All of St, Amo, Lr and Sc use the normal 3-bit encoding for the width;
rather than add Lr and Sc to the list, switch it just to exclude Ld as
the special case that's handled by the other half of the expression.

Previously LR.C and SC.C were decoded as LR.BU and SC.BU.
 2021-10-27 15:44:23 +01:00
Jonathan Woodruff
87785eb25c Don't translate invalid vaddrs in the DTLB. 2021-10-14 17:13:18 +00:00
Jonathan Woodruff
3636f6239a Use Matt's slightly cleaner version of the function. 2021-10-11 16:23:22 +00:00
Jonathan Woodruff
1b5a036c46 Two fixes: do a proper "all bits are the same" function, as well as 
prepare a capability target to pass back.
 2021-10-08 16:35:42 +00:00
Jonathan Woodruff
5d5bee3e08 Use an invalid virtual address when preventing prediction, and also 
detect invalid virtual addresses in the TLB and miss rather than proceed
with page walking.
 2021-10-08 11:00:11 +00:00
Jonathan Woodruff
81a12b89cb Move to NonPipelinedSquareRooter to hopefully fit more 
deterministically.
We're still waiting for a fixed NonPipelinedDivider.
 2021-10-07 16:28:57 +00:00
gameboo
9657339d87 "fix" non PERFORMANCE_MONITORING build 2021-09-29 18:09:06 +01:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
bc7eed67ab Did more cleaning up 2021-09-06 15:55:28 +01:00
Franz Fuchs
61d788ebc7 define No_Of_Evts in StatCounters 2021-09-03 14:14:32 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Robert Norton
0970951184 Fix decoding of lr / sc with explicit bounds. 
When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register.
 2021-09-01 10:16:49 +01:00
Robert Norton
7e2a946c4c Fix incorrect check for permitStoreLocalCap in capChecksMem. 
The check was missing a NOT and was actually checking for permitStoreGlobalCap.
 2021-08-05 12:19:50 +01:00
Robert Norton
5b23f4cea0 Fix incorrect checks in capChecksMem. 
These checks were broken in several ways:

1) a missing 'else' inverted the priority of PermitStoreViolation vs. PermitStore[Local]Cap exceptions
2) another missing 'else' inverted the priority of PermitStoreCap and PermitStoreLocalCap exceptions
3) No store checks were performed when mem_func == Amo because of the preceding if clause for loads

I decided to flatten the nested if statements by pulling out the conditions into boolean local variables. Hopefully this makes it clearer (as well as fixing the bugs).
 2021-08-05 09:33:52 +01:00
Franz Fuchs
c37c611522 Merge branch 'CHERI' into faf28_sbc_jumps 2021-07-08 17:14:27 +01:00
Franz Fuchs
224ab35679 Completed introduction of new build flag 2021-07-08 15:38:19 +01:00
Franz Fuchs
4ba377366a Introduced new build flag for transient-execution testing contracts 2021-07-08 15:28:54 +01:00
jon
849d5c57f8 Fix condition where Queue can remain "empty" when there were outstanding 
indices due to the head-1 element happening to match new requests.
This leads to "remove" when empty, leading to being "almostFull" when
there are no outstanding users that will remove anything.
 2021-07-07 11:34:29 +01:00
Franz Fuchs
db6a91e0fd mad Maps flush on reset 2021-07-06 15:19:37 +01:00
Franz Fuchs
2eb2202acd Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst 2021-06-28 07:34:57 +01:00
Franz Fuchs
fec16f64c8 Added first attempts for counting wild exceptions 2021-06-25 15:44:29 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
06e0a3d810 corrected SBC jumps counting 2021-06-22 08:40:27 +01:00
Franz Fuchs
dce934500d Added counter mechanism for wild jumps 2021-06-11 10:47:15 +01:00
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
4ae9f5346c Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-06-01 15:18:29 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Peter Rugg
88751cccba Remove hardcoded field encodings for cap loads and stores 2021-05-26 16:25:55 +01:00
Peter Rugg
913d14406e Add explicit PCC and cap JALRs 2021-05-26 16:24:41 +01:00
Peter Rugg
6450d9c33c Make JAL and JALR mode-dependent 2021-05-26 16:24:41 +01:00
Peter Rugg
657124671c Support amoswap.c 2021-05-13 23:15:25 +01:00
Peter Rugg
abc70134b1 Don't take load cap page faults if the authorising cap doesn't have load cap 2021-05-13 23:15:25 +01:00
Peter Rugg
7e77b2314b Clarify precedence in VM permission check 2021-05-05 13:32:07 +01:00