913d17224b
stable malloc
2026-04-10 00:01:22 +01:00
2d212949d9
added l1 tlb counters
2026-04-09 14:04:02 +01:00
26b025b556
enabled performance counters
2026-04-09 13:17:48 +01:00
056d4e0821
manual performance enable for dtlb
2026-04-09 12:50:48 +01:00
9f8a7eb9d8
added glibc and memaccess
2026-04-08 21:55:15 +01:00
6ded32ff2d
added glibc
2026-04-08 13:55:55 +01:00
92478b367d
pushed new logs
2026-04-01 20:37:33 +01:00
49efc6df62
sample malloc working
2026-04-01 14:48:14 +01:00
cea30a7be7
working hardware
2026-03-31 16:05:26 +01:00
fcf3390dc5
base testing
2026-03-21 18:39:01 +00:00
d03fb0cf2e
push stable benchmarks
2026-03-20 11:07:22 +00:00
debc62dfb8
further testing needed
2026-03-19 16:37:49 +00:00
3fd9a03aa6
added handler for delta to handle delta being all 1's
2026-03-19 13:22:01 +00:00
34e84f2926
sample C cheri program hybrid cap
2026-03-19 12:26:29 +00:00
6dcad25669
hardare implementation ready for testing
2026-03-18 12:41:06 +00:00
9606815dfa
enabled performance counter in CSR register
2026-03-18 11:49:19 +00:00
a0b8d07155
added tlb bypass
2026-03-13 13:19:43 +00:00
6fa2e4a36e
pass through pointer works
2026-03-12 18:11:55 +00:00
df2342139f
saving current changes
2026-03-11 16:00:42 +00:00
82a9b5231a
remote running of ISA tests
2026-03-11 14:52:10 +00:00
e558b21723
saving current changes
2026-03-05 17:40:46 +00:00
5d3f4c7d6d
added working cheri assembly
2026-03-05 15:45:05 +00:00
2e3f216448
changed reference to cheri-cap-lib
2026-02-23 12:26:57 +00:00
bf7bd16c53
adding current changes
2026-01-14 15:29:03 +00:00
c1cf362c70
changes
2026-01-10 16:14:01 +00:00
dd3336a2e0
added test for adding pages
2026-01-06 14:55:05 +00:00
6cc929d50a
added tracker to start
2025-12-24 13:12:11 +00:00
27aa16a7bf
added todo
2025-12-24 10:48:04 +00:00
28abd5de95
test traces and log file for TLB check
2025-12-23 09:34:06 +00:00
8242b86e2b
changed git modules
2025-12-01 19:43:08 +00:00
0f5520ea68
changes test benchmark
2025-12-01 19:41:40 +00:00
Jessica Clarke
a8299cfc01
CCTypes: Fix misleading bit width for MESI/Msi enum
...
4 does not fit in 2 bits. This appears to not matter in practice, as a
spot check of the generated Verilog shows 3'dN for state-related
constants, but we should not be relying on this surprisingly lax
behaviour from bsc, and who knows if there are ways in which bsc does
end up using the as-written bit width somewhere.
Fixes: 6d4644ce73
2025-11-02 14:28:02 +00:00
Rishiyur S. Nikhil
8fc12c1dee
Merge pull request #36 from h-chal/fix_rv64mi-p-access
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fix: cache full virtual address for TLB micro-cache
(cherry picked from commit a79a4502c0e689058e6a2ffafd75b507c57ed3b9)
2025-10-31 18:07:27 +00:00
PeterRugg
ed011ac0fe
Fix unseal check operand order
2025-10-01 14:48:46 +01:00
Jonathan Woodruff
e576a2cae7
Revert "Changes to make Prefetcher more deterministic, and also to report schedules."
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This reverts commit f964e1dd2c
2025-07-03 11:47:00 +01:00
Jonathan Woodruff
86c1c65261
Revert "Give commit redirect priority over branch/execute redirect."
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This reverts commit 7bc17965b6
2025-07-03 11:46:43 +01:00
Jonathan Woodruff
d8d7fc3d2b
Revert "Improve scheduling of Reorder buffer. This includes an experimental relaxation of ordering."
...
This reverts commit 1873702c81
2025-07-03 10:39:52 +01:00
Jonathan Woodruff
79556da485
Revert "Get this building, removing scheduling issue."
...
This reverts commit 5331162e3c
2025-07-03 10:37:35 +01:00
Jonathan Woodruff
78c457cdd9
Bump benchmarks subrepo to fully independent version.
2025-07-01 16:10:21 +01:00
Jonathan Woodruff
acbf07ddf0
Merge pull request #46 from CTSRD-CHERI/CHERI-benchmarks
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Cheri benchmarks
2025-06-12 10:15:45 +01:00
Jonathan Woodruff
16de32f2d4
Turn off RVFI for the benchmarks branch, as it affects CPI for some reason.
2025-06-06 14:33:55 +01:00
Jonathan Woodruff
824b575dc5
Add benchmarks directory and add script to run benchmarks in it.
2025-06-06 14:33:55 +01:00
Yuecheng-CAM
8af3b2e85a
Revert "initial commit, test compiled and run sucessfully"
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This reverts commit d025278195
2025-06-01 18:17:24 +01:00
Yuecheng-CAM
d025278195
initial commit, test compiled and run sucessfully
2025-06-01 18:14:19 +01:00
Jonathan Woodruff
5331162e3c
Get this building, removing scheduling issue.
2025-05-23 10:43:42 +01:00
Jonathan Woodruff
1873702c81
Improve scheduling of Reorder buffer. This includes an experimental relaxation of ordering.
2025-05-20 16:37:34 +01:00
Jonathan Woodruff
7bc17965b6
Give commit redirect priority over branch/execute redirect.
2025-05-20 16:34:45 +01:00
Jonathan Woodruff
f964e1dd2c
Changes to make Prefetcher more deterministic, and also to report schedules.
2025-05-20 16:32:33 +01:00
Jonathan Woodruff
852d352d04
Merge pull request #45 from CTSRD-CHERI/CHERI-cachefix
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Cheri cachefix
2025-05-20 11:36:56 +01:00
Jonathan Woodruff
63f25fb0ff
Enable > ways MSHRs by default.
2025-03-25 09:59:35 +00:00
