Cheri-research/Toooba
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Author SHA1 Message Date
jon
9d5095b076 Count CJALRs with Jrs. 2021-02-24 20:36:46 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
Peter Rugg
53eb073fb2 Don't track generated Verilog 2021-02-19 19:45:00 +00:00
jon
2f0b0c110f Use the necessary number of ports. 2021-02-19 17:38:16 +00:00
jon
b5bce1209a Revert "Revert biggest scheduling change from potentially problematic commit." 
This one does not actually build with the new BSC compiler.  I forgot to
test the hardware build (with GDB), which is where we have the problem.
This reverts commit b4308e9a6e.
 2021-02-19 17:38:16 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
Peter Rugg
47c94b5a34 Map more RAM in SSITH build 2021-02-19 09:25:41 +00:00
jon
b4308e9a6e Revert biggest scheduling change from potentially problematic commit. 
This still builds with the new BSC compile.
 2021-02-18 15:18:58 +00:00
jon
1fbf786294 Add to synthesis file set. 2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7 Add one more missing file and clean up some duplicates. 2021-02-17 18:37:52 +00:00
jon
0f3fd15d41 Initial implementation of map of HPM counters into supervisor and user 
mode.  This version just unconditionally exposes them.
 2021-02-17 17:07:53 +00:00
jon
5ba685b541 Try harder to remove all copies of references to old files. 2021-02-17 16:57:01 +00:00
jon
7a59cad288 Remove more no-longer-generated files from component.xml 2021-02-17 15:54:27 +00:00
jon
9d2acbd96d Bump to latest version of Bluestuff. 2021-02-17 14:59:31 +00:00
jon
059f189bba Attempt to add all current source files to componenet.xml. 2021-02-17 14:35:49 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00
Marno van der Maas
e3b776a81f Clarified supported versions of verilator 2021-02-12 09:49:17 +00:00
jon
9e36ff95cd Roll back accidental commit of experimental change. 2021-02-11 12:22:00 +00:00
jon
96be5802a0 Bump BlueStuff with workaround. 2021-02-10 17:23:46 +00:00
jon
40ea082310 Some updates to build with the new bsc compiler. 2021-02-10 17:22:26 +00:00
jon
9dd2dd9c77 Bump cheri-cap-lib. 2021-02-10 17:22:26 +00:00
Marno
65d0edd722 Bump BlueStuff to fix compiler error with new bsc 2021-02-10 14:07:02 +00:00
Peter Rugg
a78d09c522 Add ifdefs for GDB control on helper functions 2021-02-08 14:49:13 +00:00
Jessica Clarke
fb5339e9ca Adapt the PLIC instantiation and wiring to support multiple cores 2021-01-31 17:54:43 +00:00
Peter Rugg
cedb4c279d Ensure the MMIO platform issues aligned requests by changing the AXI4_Size field based on the byte enables 2021-01-31 17:34:35 +00:00
Peter Rugg
44e19afbf3 Fix MMIO bug missing uncached instruction bytes with certain alignments 2021-01-30 15:22:22 +00:00
Peter Rugg
f800cdeb77 Prevent spurious warnings 2021-01-30 15:21:38 +00:00
Peter Rugg
d340066f6f Multicore debug cleanups 2021-01-21 20:51:02 +00:00
Peter Rugg
30e7090213 Multicore debug-module 2021-01-21 20:30:07 +00:00
Peter Rugg
3417fb454e Revert "Provide opt-in wedge debugging info" - some missed changes 
This reverts commit 68d3bd484e.
 2021-01-21 20:30:07 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs" 
This reverts commit 5e9b478371.
 2021-01-19 21:39:59 +00:00
Jessica Clarke
6c98dcb3d8 src_SSITH_P3: Delete stray file references 
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
 2021-01-13 00:59:46 +00:00
Jessica Clarke
1fb31bb255 src_SSITH_P3: Another open-source bsc fix 2021-01-11 21:34:11 +00:00
Jessica Clarke
7ae8689ce5 src_SSITH_P3: Fix build with open-source bsc 
bsc-contrib puts these under AMBA_TLM3.
 2021-01-11 20:57:50 +00:00
Jessica Clarke
4a0c8fe7d2 PLIC: Update comment after previous commit 2020-12-21 13:37:01 +00:00
Jessica Clarke
ac6244181a PLIC: Allow multiple interrupts to be claimed but not completed 
Whilst the current PLIC spec is hard to decipher, the older v1.9
privileged spec is clearer. The intent is that each interrupt is
independent and so claims and completions can be overlapped (e.g. as
done by FreeBSD if deferring an interrupt handler). This is
approximately expressed in the spec by:

  The PLIC can perform a claim at any time and the claim operation is
  not affected by the setting of the priority threshold register.

  ...

  The PLIC does not check whether the completion ID is the same as the
  last claim ID for that target. If the completion ID does not match an
  interrupt source that is currently enabled for the target, the
  completion is silently ignored.

Thost last two sentences make it sound like the completion ID not
matching the last claim ID is a thing to ignore, but in fact they are
entirely independent statements. This can be confirmed by reading the
source for the Rocket and QEMU PLICs, which have none of the stricter
requirements of the Bluespec PLIC implementation.

This should fix running FreeBSD after r362977, which started to
correctly delay the completion of interrupts until after deferred
handlers had completed (as opposed to after they had been queued).
 2020-12-21 13:32:06 +00:00
Jessica Clarke
6b55d30a8e PLIC: Restore upstream whitespace 2020-12-21 13:32:06 +00:00
Jessica Clarke
e3f94224de Revert "Cause two surprising conditions to not throw slave errors as this is not" 
This reverts commit 4131dcd073.
 2020-12-21 13:03:13 +00:00
Jonathan Woodruff
92ca72a6e2 Fix build error by providing default. 2020-12-18 17:55:18 +00:00
Jonathan Woodruff
84d60d03b1 Merge pull request #6 from nwf/capdirty 
CHERI ISAv8 CapDirty fault priority fix
 2020-12-18 16:48:56 +00:00
jon
f86d4d9dc0 Add counter support to ITLB. 2020-12-17 17:57:43 +00:00
jon
4ddcaff497 Support for data TLB counters. 2020-12-17 16:52:45 +00:00
Jonathan Woodruff
4dd0a73051 Port to internal AXI interfaces for the debug module. 2020-12-17 15:02:05 +00:00
jon
bab989d6d2 Support for stat counters from the tag controller. 
The order of the events is very not tested; 50% chance of being correct.
 2020-12-17 12:38:52 +00:00
jon
4131dcd073 Cause two surprising conditions to not throw slave errors as this is not 
specified and causes kernel panics.  Hopefully the details of what
should happen in these cases is correct, but we shall see...
 2020-12-17 12:37:45 +00:00
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00