Cheri-research/Toooba
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f83d7b15544f8e148ef5dceeec0334e3452f9587
Commit Graph

336 Commits

Author SHA1 Message Date
Franz Fuchs
f83d7b1554 Added missing ifdefs 2021-06-24 08:35:21 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
c9df8da1b1 Corrected SBC counting 2021-06-23 12:47:34 +01:00
Franz Fuchs
23913a50e0 Improved code for detecting SBC violations 2021-06-23 08:00:42 +01:00
Franz Fuchs
76cdc13a50 Added counting code for return instructions 2021-06-22 18:01:32 +01:00
Franz Fuchs
8f45238b5d implemented method returning the trans exe events 2021-06-22 08:49:40 +01:00
Franz Fuchs
06e0a3d810 corrected SBC jumps counting 2021-06-22 08:40:27 +01:00
Franz Fuchs
a60bed404a Added new counting for branching instructions 2021-06-11 17:09:21 +01:00
Franz Fuchs
dce934500d Added counter mechanism for wild jumps 2021-06-11 10:47:15 +01:00
Franz Fuchs
c51af07278 Collect all architectural jump targets (the first 16) in a bag to enable verifying properties 2021-06-10 18:55:00 +01:00
Franz Fuchs
2572fdceba Added documentation for rename counter and removed unnecessary display messages 2021-06-08 15:03:12 +01:00
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
4ae9f5346c Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-06-01 15:18:29 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Peter Rugg
1b5f4ee9e0 Add capability-aware compressed decoding 2021-05-26 16:25:55 +01:00
Peter Rugg
88751cccba Remove hardcoded field encodings for cap loads and stores 2021-05-26 16:25:55 +01:00
Peter Rugg
913d14406e Add explicit PCC and cap JALRs 2021-05-26 16:24:41 +01:00
Peter Rugg
6450d9c33c Make JAL and JALR mode-dependent 2021-05-26 16:24:41 +01:00
Peter Rugg
657124671c Support amoswap.c 2021-05-13 23:15:25 +01:00
Peter Rugg
abc70134b1 Don't take load cap page faults if the authorising cap doesn't have load cap 2021-05-13 23:15:25 +01:00
Peter Rugg
7e77b2314b Clarify precedence in VM permission check 2021-05-05 13:32:07 +01:00
Peter Rugg
e7258f0f22 Plumb through info on whether a load is capWidth to the TLB 2021-05-05 13:32:07 +01:00
jon
b8d86df2d0 Guard Meltdown_CF protection (such as it is) with ifdef rather than just 
comment it out.
 2021-05-04 11:29:36 +01:00
jon
2dccf1b557 Add (not-enabled-by-defaul) Meltdown-CF fix which resolves CUnseal, but not any 
of the ones that require a bounds-check.
This isn't enabled by default so that we can evaluate the seriousness of
the vulnerabilities.
 2021-04-29 17:46:39 +01:00
Peter Rugg
48e22af43e Factor out PTE cap invalid check 2021-04-29 16:02:30 +01:00
Peter Rugg
005ba1bd6f Add LoadCapPageFault exception cases 2021-04-29 16:02:30 +01:00
Peter Rugg
1eef5d2979 Still advance the DII stream on instruction fetch PTE fault (with jrtc27) 2021-04-29 16:02:30 +01:00
Peter Rugg
3b07a2a17c Add revocation 3.0 bits 2021-04-29 16:02:30 +01:00
jon
7cefaacb86 Remove wayward disabling of consistency flush case for the weak memory 
model.
 2021-04-21 10:44:31 +01:00
jon
2c41fcd7fb Fix bug and improve expression by using Int. 2021-04-12 12:48:49 +01:00
jon
4776bc0a11 Double-train on killing a load (still decrement by one on success). 
This combo got the best performance overall (I tested triple and
quadruple training).
 2021-04-12 06:34:16 +01:00
jon
8e3fd534f9 Do negative training when we encounter a load that has previously been 
killed, but was not killed this time.
 2021-04-10 08:47:05 +01:00
jon
aa9e57ce10 Fix bug so that we actually start at minBound. 
(Map defaults to unpack(0), so for an Int, our first updateFunc will add
one to zero and it won't be much different than before.)
 2021-04-10 07:54:39 +01:00
jon
6b871c0442 Use a saturating add before being conservative with issuing loads. 2021-04-09 16:21:55 +01:00
Peter Rugg
fcea5365f6 Initial implementation CLoadTags 
This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
 2021-04-08 17:08:15 +01:00
Peter Rugg
b232272ad1 Treat CCSeal with an out-of-bounds capability as a move 
See 2d7ae22c0a for corresponding Sail change

This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
 2021-04-08 13:08:46 +01:00
jon
12ac14c1ca Move to config registers here as this affects scheduling. 2021-04-07 17:47:49 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Franz Fuchs
6e157fff5a Small improvement of BTB changes made by Jon and myself 2021-04-01 09:08:47 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
84271b2712 Changes to build (and run?) with TSO_MM. 2021-03-29 12:03:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00
Jonathan Woodruff
2bfe25dfad Update Map.bsv 
Remove unused function.
 2021-03-22 20:28:34 +00:00
jon
d351eeee11 Increase BTB to 1024 entries. 
(On FPGA we can make this as large as we like, but returns diminish.
This one has a chance of being reasonable for ASIC I guess?)
 2021-03-22 18:20:22 +00:00
jon
30bd5e7f46 Allow entries in the load kill predictor to be "False" so that they can 
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.

Remove debugging prints.
 2021-03-22 18:14:33 +00:00
jon
791927f852 Prediction for whether a load will have an aliasing store. 2021-03-22 18:14:33 +00:00