Jonathan Woodruff
f86ea0203d
Potential workaround for issue with vcu118 memory bus error.
...
Just use the same ID for all outstanding requests such that all requests
are in-order.
Previously we were working fine with requests serialised; requests
are now fully pipelined and out-of-order.
This change should roll back to in-order, but still pipelined.
This only affects the top-level used in the GFE (vcu118).
This design is working on the DE10 setup, so the issue is not
believed fundamental with CoreW.
2024-04-04 14:09:16 +01:00
Peter Rugg
5818a886dd
Factor out delay shim
2023-07-15 22:37:45 +01:00
Peter Rugg
d509ab0fab
Mask off address bits in latency shim
2023-07-15 22:37:45 +01:00
Peter Rugg
5414a13d3b
Add prints for latency rules
2023-07-15 22:37:45 +01:00
Peter Rugg
f71f650023
Allow dynamic latency config
2023-07-15 22:37:45 +01:00
Peter Rugg
d17d3135bb
Add error clear implementation for delayShim
2023-07-15 22:37:45 +01:00
Peter Rugg
23b471e0ae
Increase number of outstanding transactions in delayShim
2023-07-15 22:37:45 +01:00
Peter Rugg
1a94699de6
Delay non-burst channels
2023-07-15 22:37:45 +01:00
Peter Rugg
e6370f46f6
Remove unnecessary type
2023-07-15 22:37:45 +01:00
Peter Rugg
f7755d0e58
Increase DRAM latency for realism
2023-07-15 22:37:45 +01:00
gameboo
b3a75cfeac
Bump BlueStuff and make use of Makefile fragment
2023-06-22 16:40:23 +01:00
Jonathan Woodruff
5dfedf5b4c
Don't build with BSC protection by default.
2023-03-08 11:30:33 +00:00
Peter Rugg
eb755801eb
Revert "Revert "Use wide to narrow AXI4 shim""
...
This reverts commit 93180fbe25
2023-03-01 14:38:13 +00:00
Peter Rugg
93180fbe25
Revert "Use wide to narrow AXI4 shim"
...
This reverts commit be91801982
2023-02-17 11:16:20 +00:00
Peter Rugg
5f5e391e32
Connect ndm reset up in src_SSITH_P3 build
2023-02-10 18:12:33 +00:00
Jonathan Woodruff
5c6e348788
Missing width extensions.
2023-01-17 16:11:52 +00:00
Jonathan Woodruff
f5450a1c06
Extend ID field to match current design.
...
This is likely to be cause of lockup in hardware.
2023-01-16 17:45:07 +00:00
gameboo
be91801982
Use wide to narrow AXI4 shim
2023-01-06 16:07:56 +00:00
Jonathan Woodruff
06a9221bb1
Changes for GFE hardware build with 512-bit bus.
2022-11-23 13:29:46 +00:00
Alexandre Joannou
95f554dad1
removed coreW from component.xml
2022-08-16 12:44:00 +00:00
Alexandre Joannou
a4606c6761
Brought the src_SSITH_P3 folder up to date
2022-08-15 16:18:23 +00:00
Alexandre Joannou
bb62b703c8
Address some rebase nonsense
2022-08-15 16:18:23 +00:00
Franz Fuchs
1bea2c6af2
added missing character to Makefile
2022-07-06 08:31:43 +01:00
Franz Fuchs
0dd65a937f
enabled full BSC build
2022-07-05 12:09:26 +01:00
Franz Fuchs
92b096472a
do configuration for base protection version of Toooba
2022-07-01 10:19:26 +01:00
Franz Fuchs
45b3eaf09c
correct SSITH Makefile
2022-06-30 12:57:07 +01:00
Franz Fuchs
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
2022-06-30 12:55:53 +01:00
Franz Fuchs
82adf5e869
attempt to get new performance numbers
2022-06-29 17:42:38 +01:00
Franz Fuchs
40cfd0e97c
removed PUSH_DELAY from gfe-synth build
2022-06-16 08:56:07 +01:00
Franz Fuchs
1ab18ab6ee
full BSC protection for gfe-synth build
2022-06-15 06:07:36 +01:00
Franz Fuchs
b79a228093
added no prediction STL predictor
2022-06-08 12:23:35 +01:00
Jonathan Woodruff
25013c9713
Revert to including performance improvements by default.
2022-03-29 10:26:35 +00:00
Jonathan Woodruff
c273314084
Remove all BSC protections in an attempt to get a baseline bitfile for
...
that work.
2022-03-29 10:17:12 +00:00
Jonathan Woodruff
163ca1d099
Use only parameters that improve performance.
2022-03-25 14:08:43 +00:00
Jonathan Woodruff
ad7bcbb559
Temprarily remove all protections for a baseline bitfile.
2022-03-25 11:09:32 +00:00
Jonathan Woodruff
3248e42485
Temporarily turn off late push so we can run benchmarks for non-push
...
case.
2022-03-21 10:14:08 +00:00
Jonathan Woodruff
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop
...
while waiting for a push.
2022-03-07 17:52:11 +00:00
Jonathan Woodruff
6d65de5c88
Experimentally remove delayed RSB_PUSH for synthesis.
2022-02-24 11:49:35 +00:00
Jonathan Woodruff
6ea972931d
Add missing verilog file that is inadvertantly used.
2022-02-23 16:46:43 +00:00
Jonathan Woodruff
28646b252d
Add BSC protections to the hardware makefile.
2022-02-23 11:43:41 +00:00
Franz Fuchs
df74a71d61
changed _Synth to _Sig following the new convention in BlueStuff
2021-09-30 15:02:47 +01:00
Franz Fuchs
b4fe3ee93c
adjusted SSITH_P3 Makefile to new version of HPM Events
2021-09-30 13:33:26 +01:00
Jonathan Woodruff
c379a7a293
Changes to build with the new stat counters.
2021-09-24 13:18:55 +00:00
Peter Rugg
ac89600601
Add missing TSO dummy store buffer to component.xml
2021-04-23 16:33:26 +01:00
Peter Rugg
10b5cd7ad7
Switch to TSO
2021-04-22 18:22:02 +01:00
Peter Rugg
53549e0dbc
Set number of cores using RISCY config instead of manual define
...
This was leading to -D NUM_CORES=2 -D NUM_CORES=1 in the command.
The NUM_CORES=2 seems to have been winning, but this is obviously
far from ideal.
2021-04-12 13:10:12 +01:00
Marno van der Maas
3f059cbd94
Added note on bsc-contrib dependency to SSITH readme
2021-04-07 11:53:48 +01:00
Marno
47cddd8ec9
Reverted back to using FPGA specific memory addresses
2021-03-19 15:54:53 +00:00
Marno
dbc1443bf2
Also using new tagsparams API in SSITH build
2021-03-19 15:30:11 +00:00
Peter Rugg
057964e940
Some more tagsparam makefile fixes
2021-03-18 11:09:26 +00:00
