Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
1,175 Commits 7 Branches 0 Tags
master
Commit Graph

58 Commits

Author SHA1 Message Date
Jonathan Woodruff
1b9d498e95 Standardise on using underscores in directory names in makefiles. 2024-05-17 11:21:42 +01:00
Jonathan Woodruff
2c648eb1ed Restructure makefiles so that all common and branch-specific flags/files 
are in Include_RISCY_Config.mk so that this can be included from an
external repo without replicating Toooba branch-specific flags in that
repo.
 2024-05-15 10:01:28 +01:00
gameboo
b3a75cfeac Bump BlueStuff and make use of Makefile fragment 2023-06-22 16:40:23 +01:00
Jonathan Woodruff
5dfedf5b4c Don't build with BSC protection by default. 2023-03-08 11:30:33 +00:00
Jonathan Woodruff
06a9221bb1 Changes for GFE hardware build with 512-bit bus. 2022-11-23 13:29:46 +00:00
Alexandre Joannou
a4606c6761 Brought the src_SSITH_P3 folder up to date 2022-08-15 16:18:23 +00:00
Franz Fuchs
1bea2c6af2 added missing character to Makefile 2022-07-06 08:31:43 +01:00
Franz Fuchs
0dd65a937f enabled full BSC build 2022-07-05 12:09:26 +01:00
Franz Fuchs
92b096472a do configuration for base protection version of Toooba 2022-07-01 10:19:26 +01:00
Franz Fuchs
45b3eaf09c correct SSITH Makefile 2022-06-30 12:57:07 +01:00
Franz Fuchs
c85b13c5af added MELTDOWN_CF ifdef and enabled it 2022-06-30 12:55:53 +01:00
Franz Fuchs
82adf5e869 attempt to get new performance numbers 2022-06-29 17:42:38 +01:00
Franz Fuchs
40cfd0e97c removed PUSH_DELAY from gfe-synth build 2022-06-16 08:56:07 +01:00
Franz Fuchs
1ab18ab6ee full BSC protection for gfe-synth build 2022-06-15 06:07:36 +01:00
Franz Fuchs
b79a228093 added no prediction STL predictor 2022-06-08 12:23:35 +01:00
Jonathan Woodruff
25013c9713 Revert to including performance improvements by default. 2022-03-29 10:26:35 +00:00
Jonathan Woodruff
c273314084 Remove all BSC protections in an attempt to get a baseline bitfile for 
that work.
 2022-03-29 10:17:12 +00:00
Jonathan Woodruff
163ca1d099 Use only parameters that improve performance. 2022-03-25 14:08:43 +00:00
Jonathan Woodruff
ad7bcbb559 Temprarily remove all protections for a baseline bitfile. 2022-03-25 11:09:32 +00:00
Jonathan Woodruff
3248e42485 Temporarily turn off late push so we can run benchmarks for non-push 
case.
 2022-03-21 10:14:08 +00:00
Jonathan Woodruff
064cd22114 Inteligently delay Decode (for up to 8 cycles) if we encounter a pop 
while waiting for a push.
 2022-03-07 17:52:11 +00:00
Jonathan Woodruff
6d65de5c88 Experimentally remove delayed RSB_PUSH for synthesis. 2022-02-24 11:49:35 +00:00
Jonathan Woodruff
28646b252d Add BSC protections to the hardware makefile. 2022-02-23 11:43:41 +00:00
Franz Fuchs
b4fe3ee93c adjusted SSITH_P3 Makefile to new version of HPM Events 2021-09-30 13:33:26 +01:00
Jonathan Woodruff
c379a7a293 Changes to build with the new stat counters. 2021-09-24 13:18:55 +00:00
Peter Rugg
10b5cd7ad7 Switch to TSO 2021-04-22 18:22:02 +01:00
Peter Rugg
53549e0dbc Set number of cores using RISCY config instead of manual define 
This was leading to -D NUM_CORES=2 -D NUM_CORES=1 in the command.
The NUM_CORES=2 seems to have been winning, but this is obviously
far from ideal.
 2021-04-12 13:10:12 +01:00
Marno
47cddd8ec9 Reverted back to using FPGA specific memory addresses 2021-03-19 15:54:53 +00:00
Marno
dbc1443bf2 Also using new tagsparams API in SSITH build 2021-03-19 15:30:11 +00:00
Peter Rugg
057964e940 Some more tagsparam makefile fixes 2021-03-18 11:09:26 +00:00
Peter Rugg
80fb97cc62 Take Bluestuff-ified Giraffe_IFC from Flute 2021-03-15 12:25:38 +00:00
Peter Rugg
395a9d1c02 Remove unused non-existent libraries from ssith Makefile 2021-03-15 11:26:24 +00:00
Peter Rugg
0e1e2249a6 Default to dual-core builds 2021-03-04 11:54:35 +00:00
Jessica Clarke
9dc27542f3 Use order-only prerequisites for directories 
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
 2021-02-28 04:14:54 +00:00
Peter Rugg
53eb073fb2 Don't track generated Verilog 2021-02-19 19:45:00 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00
Peter Rugg
f800cdeb77 Prevent spurious warnings 2021-01-30 15:21:38 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Jessica Clarke
1fb31bb255 src_SSITH_P3: Another open-source bsc fix 2021-01-11 21:34:11 +00:00
Jessica Clarke
7ae8689ce5 src_SSITH_P3: Fix build with open-source bsc 
bsc-contrib puts these under AMBA_TLM3.
 2021-01-11 20:57:50 +00:00
Jessica Clarke
956c9686a6 src_SSITH_P3: Optimise unspecified values 
We have a lot of ?s floating around that needlessly constrain logic. As
with Flute, enable optimisations on these in the hope that timing and/or
area improve further.
 2020-07-14 17:53:01 +01:00
Jessica Clarke
68d3bd484e Provide opt-in wedge debugging info 
When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
 2020-07-07 23:59:35 +01:00
Jessica Clarke
badf5c8e37 Include xCHERI in ARCH and build directory names 
Also use RVFI_DII not RVFIDII in the directory names.

This makes everything match Piccolo/Flute rather than having Toooba be a
weird, inconsistent and plain wrong.
 2020-07-05 21:41:28 +01:00
Jessica Clarke
0b0b863baa Replace home-grown dependency script with Bluespec-provided makedepend.tcl 
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
 2020-07-05 21:26:18 +01:00
Peter Rugg
8778369fe5 Merge remote-tracking branch 'upstream/master' into CHERI 2020-06-17 13:01:41 +01:00
Peter Rugg
4f4bbbbdcb Add new TagController parameters to synth makefile 2020-06-17 11:40:23 +01:00
Peter Rugg
962ade1092 Fixes for synthesis 2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909 Remove Tandem verification 2020-06-03 22:28:31 +01:00
rsnikhil
a6a227ed66 Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...) 
Amendment: RegUNInit.v updated, removing an extraneous RST line.
 2020-03-13 16:38:54 -04:00
Niraj N Sharma
6f5d079e7c Modified synth and sim compile options in the Makefile 
Regenerated synth and sim RTLs
 2020-02-22 17:51:13 +05:30