Cheri-research/Toooba
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Author SHA1 Message Date
jon
8a13b866d7 Bump bluestuff to the one with generalised report width. 2020-12-02 15:31:49 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
742c4c5c92 Bump Bluestuff. 2020-12-01 18:03:44 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00
Nathaniel Filardo
6e4c378d4d CHERI ISAv8 CapDirty fault priority fix 
Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
 2020-11-06 19:15:47 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Peter Rugg
bf77ac74ba Fix performance reporting requests for multicore 2020-11-04 12:11:31 +00:00
Peter Rugg
61b88ef987 Generate elf files the correct size 2020-11-02 11:23:07 +00:00
Marno van der Maas
328592b068 Added missing slash in readme 2020-10-29 15:45:17 +00:00
Jonathan Woodruff
29168574ca Revert "Sort of support 2 cores for starting and halting." 
This reverts commit b4b7718aa2.
 2020-10-16 15:44:53 +01:00
jon
b4b7718aa2 Sort of support 2 cores for starting and halting. 2020-10-08 15:09:23 +01:00
PeterRugg
844bfd5e79 Merge pull request #5 from nwf/capdirty 
Add CHERI PTE CapDirty flag
 2020-10-02 17:17:24 +01:00
Marno van der Maas
ed9541e8d0 Put all dirs for source description in code blocks 2020-10-02 13:09:51 +01:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00
jon
9508eada79 Change to allow 1-way superscalar to build without error. 2020-09-17 14:40:46 +01:00
jon
1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. 
(Previously we ran into the limit of ports on the regFiles holding state
in the BTB.  This uses a vector of regFiles with a vector of interfaces,
which is logically the same but might produce multiple copies of state.)
 2020-09-16 11:42:19 +01:00
jon
96afb0a7f5 FIFO optimisation both for build time (and possibly condition 
complexity?) and for throughput.
 2020-08-13 17:33:46 +01:00
jon
4c74d27e4e Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:31:30 +01:00
jon
7a93056b8b Increase the capacity of f32d to enable full throughput. 
I don't know why this is necessary, but this allows performance parity
with the baseline.
 2020-08-11 15:30:03 +01:00
jon
9230fcc3b4 Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:25:12 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
jon
3b97fbe255 Rename last->prev for clarity. 2020-07-31 13:46:33 +01:00
jon
f63673c3f3 First working implementation of the new instruction picker. 
Evidence of "working" is passing TestRIG to a cursory depth including
compressed instructions and running CoreMark in simulation.
This one appears to be 2.5% slower than the existing design in CoreMark,
so some optimisation should be done.  We expect it to be a bit faster
than the original due to more flexibility in decoding instructions from
different fetch units together.
 2020-07-31 11:25:28 +01:00
jon
3a9e76c1fd Fix bug where the wrong bounds were attached to a mispredicted half of 
an instruction.
 2020-07-29 12:32:28 +01:00
jon
8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." 
This reverts commit 4fe24c9cd5.
 2020-07-29 11:40:00 +01:00
jon
4fe24c9cd5 Remove the special flush from the Fetch3 stage. 
This is an intermediate simplification for moving to SupFifo-based picking.
 2020-07-29 07:40:15 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00
Jessica Clarke
73dedec309 FetchStage: Use map rather than for loop 
Also add some spaces in the following line.
 2020-07-24 20:02:10 +01:00
Jessica Clarke
0b3ad23c24 Fix typo 2020-07-24 19:10:11 +01:00
Jessica Clarke
1bad5b080b Various updates to README.md 
* Fix the arch string
 * Document the RVFI-DII build directories
 * Don't tell people to build RTL using them
 * Bluesim build configurations exist
 2020-07-24 19:06:56 +01:00
Jessica Clarke
44d49a52c0 Drop removed CHERI directory from README.md (Closes: #3) 
27947f4df7 moved the SCRs into the main
CSR register file, and that was the only thing in this directory.
 2020-07-24 18:47:26 +01:00
jon
40af067a71 Fix RVFI_DII build in the presence of 2-byte bundles. 2020-07-24 17:30:29 +01:00
jon
1f968b0c07 2-byte aligned instruction memory to simplify compressed instruction 
fetch.
 2020-07-24 12:38:37 +01:00
Peter Rugg
ecce475b97 Merge branch 'mem_perm_checks' into CHERI 2020-07-23 16:53:14 +01:00
Peter Rugg
27082ee2a9 Report writes to PCC as illegal instruction, not ASR violation 2020-07-23 15:40:28 +01:00
Peter Rugg
97d89086a6 Bump cheri-cap-lib 2020-07-23 11:20:30 +01:00
Peter Rugg
e8aa873c2e Prevent 'insufficient type info' warning 2020-07-23 11:18:31 +01:00
Peter Rugg
a6b40e946b Prevent using CCSeal to 'seal over' other types 2020-07-23 11:18:07 +01:00
Peter Rugg
c693462f6b Add tag-clearing due to cap load perm and PTE bits 2020-07-22 15:54:49 +01:00
Peter Rugg
0040b05ada Add page table cap store checking 2020-07-21 16:02:37 +01:00
Jessica Clarke
2f4f5ca838 FetchStage: Reduce diff to upstream 2020-07-21 14:36:36 +01:00
Jessica Clarke
0516db5e8d Bump BSV-RVFI-DII and refactor to support new parcel-based interface 
This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
 2020-07-21 14:36:36 +01:00
jon
7d98946103 Working compressed instruction support. 2020-07-20 19:49:52 +01:00
jon
d7a4d3497b Keep unaligned instruction fetch from breaking DII. 2020-07-17 16:39:13 +01:00
jon
4d2f971767 Assign the correct PC to fetched instructions. 2020-07-17 11:07:19 +01:00
Jessica Clarke
72f49a1109 Regenerate verilog 2020-07-16 19:35:51 +01:00
Jessica Clarke
2b8e5f1dad FetchStage: Inline unnecessary local variable 2020-07-16 18:13:43 +01:00