Cheri-research/Toooba
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103835db72ba356feaa1dc21ca5e795b58ffec00
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Author SHA1 Message Date
jon
103835db72 Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-04-08 14:41:48 +01:00
jon
0be771df4c Bump TagController to one with 32KiB cache. 2021-04-08 14:40:49 +01:00
Peter Rugg
b232272ad1 Treat CCSeal with an out-of-bounds capability as a move 
See 2d7ae22c0a for corresponding Sail change

This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
 2021-04-08 13:08:46 +01:00
jon
12ac14c1ca Move to config registers here as this affects scheduling. 2021-04-07 17:47:49 +01:00
Marno van der Maas
3f059cbd94 Added note on bsc-contrib dependency to SSITH readme 2021-04-07 11:53:48 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
Franz Fuchs
6e157fff5a Small improvement of BTB changes made by Jon and myself 2021-04-01 09:08:47 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
84271b2712 Changes to build (and run?) with TSO_MM. 2021-03-29 12:03:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00
Jonathan Woodruff
2bfe25dfad Update Map.bsv 
Remove unused function.
 2021-03-22 20:28:34 +00:00
jon
d351eeee11 Increase BTB to 1024 entries. 
(On FPGA we can make this as large as we like, but returns diminish.
This one has a chance of being reasonable for ASIC I guess?)
 2021-03-22 18:20:22 +00:00
jon
30bd5e7f46 Allow entries in the load kill predictor to be "False" so that they can 
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.

Remove debugging prints.
 2021-03-22 18:14:33 +00:00
jon
791927f852 Prediction for whether a load will have an aliasing store. 2021-03-22 18:14:33 +00:00
Marno
47cddd8ec9 Reverted back to using FPGA specific memory addresses 2021-03-19 15:54:53 +00:00
Marno
dbc1443bf2 Also using new tagsparams API in SSITH build 2021-03-19 15:30:11 +00:00
Marno
c38f0e8488 Using new tagparams.py that explicitly warns about overlapping tag and data memory regions 2021-03-19 11:22:40 +00:00
Marno van der Maas
5d7b224d8b Added TagTableStructure.bsv as dependency for .depends.mk in verilator build as well 2021-03-18 11:36:46 +00:00
Peter Rugg
057964e940 Some more tagsparam makefile fixes 2021-03-18 11:09:26 +00:00
Marno
e759077259 Made sure TagTableStructure.bsv is present upon regenration of .depends.mk 2021-03-18 10:47:15 +00:00
Marno
e7d0a6adf6 Removing TagTableStructure.bsv and .depends.mk on clean 2021-03-17 16:53:03 +00:00
Marno
df6cc12abb Removed TagTableStructure.bsv files from repo because these are now automatically generated 2021-03-17 16:01:16 +00:00
Marno
db57e909fc Added calling tagsparams.py in Include_Common.mk 2021-03-17 15:56:03 +00:00
Franz Fuchs
c5a0d38a63 Enabled HPM by default in builds/RV64ACDFIMSUxCHERI_Toooba_verilator/ 2021-03-16 13:19:47 +00:00
Peter Rugg
80fb97cc62 Take Bluestuff-ified Giraffe_IFC from Flute 2021-03-15 12:25:38 +00:00
Peter Rugg
395a9d1c02 Remove unused non-existent libraries from ssith Makefile 2021-03-15 11:26:24 +00:00
Jessica Clarke
d722d851d9 verilator_config.vlt: Hopefully suppress deprecation warnings for 4.026 2021-03-11 14:11:38 +00:00
jon
8de3cfffeb Remove debug print statements. 2021-03-10 17:03:35 +00:00
Jonathan Woodruff
6ef565e56c Fix bugs in previous commit due to test build not using performance 
counters.
 2021-03-09 16:05:01 +00:00
jon
1ef2d0cbeb Include both execute redirect and commit redirect in "redirect" counter. 2021-03-09 15:57:15 +00:00
Marno van der Maas
da1fd3781a Correction in testbench section 2021-03-09 10:58:56 +00:00
Marno van der Maas
f3f52d85ea Added links to RiscyOO and CHERI 2021-03-09 10:55:17 +00:00
Marno van der Maas
d3f40216a9 Made the unimplemented notation consistent 2021-03-09 10:46:55 +00:00
jon
fe7977e4e9 Fix typo when removing commented out code. 2021-03-06 07:24:49 +00:00
jon
8da520175f Use an (unguarded) BRAM in the Btb. 
Also, assume that a target that is not taken should be removed from the
Btb.  (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
 2021-03-06 07:19:50 +00:00
jon
4b411bf752 A Btb with 1/4 the storage that will (hopefully) infer as BRAM. 2021-03-05 12:14:26 +00:00
jon
7aea0325fc Add cycles to commit instruction reports to help with performance 
debugging.
 2021-03-05 12:12:33 +00:00
jon
89f0c3a45f Reduce verbosity. 2021-03-05 12:11:49 +00:00
Franz Fuchs
39e895ca4e added documentation of hardware performance monitoring events 
This document lists all implemented events and gives a short explanation
of what counting these events means.
 2021-03-04 16:45:02 +01:00
jon
6ea387f744 Fix performance bug in PC compression where we execute across a page 
boundary.
 2021-03-04 14:41:50 +00:00
Peter Rugg
0e1e2249a6 Default to dual-core builds 2021-03-04 11:54:35 +00:00
Jonathan Woodruff
db08e96596 Add Btb to the component.xml. 2021-03-03 20:27:31 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
9dc27542f3 Use order-only prerequisites for directories 
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
 2021-02-28 04:14:54 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00