Franz Fuchs
1bea2c6af2
added missing character to Makefile
2022-07-06 08:31:43 +01:00
Franz Fuchs
0dd65a937f
enabled full BSC build
2022-07-05 12:09:26 +01:00
Franz Fuchs
92b096472a
do configuration for base protection version of Toooba
2022-07-01 10:19:26 +01:00
Franz Fuchs
45b3eaf09c
correct SSITH Makefile
2022-06-30 12:57:07 +01:00
Franz Fuchs
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
2022-06-30 12:55:53 +01:00
Franz Fuchs
9b0e5c4334
Merge branch 'scc' into CHERI
2022-06-30 12:34:15 +01:00
Franz Fuchs
82adf5e869
attempt to get new performance numbers
2022-06-29 17:42:38 +01:00
Franz Fuchs
40cfd0e97c
removed PUSH_DELAY from gfe-synth build
2022-06-16 08:56:07 +01:00
Franz Fuchs
1ab18ab6ee
full BSC protection for gfe-synth build
2022-06-15 06:07:36 +01:00
Peter Rugg
fb259583dc
Attempt to clear tag on exception path before forwarding.
...
This is likely to be bad for timing, but might just work at 25MHz.
2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a
corrected ifdef in STLPred.bsv
2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093
added no prediction STL predictor
2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa
added STL predictor module and moved state from SplitLSQ to it
2022-06-08 12:04:25 +01:00
Peter Rugg
b113d05095
Prioritise misaligned over RVFIDII load access fault
2022-05-18 14:59:43 +01:00
Franz Fuchs
fd639f4b22
added typedef for static number in Ras.bsv
2022-05-14 17:16:40 +01:00
Jonathan Woodruff
25013c9713
Revert to including performance improvements by default.
2022-03-29 10:26:35 +00:00
Jonathan Woodruff
c273314084
Remove all BSC protections in an attempt to get a baseline bitfile for
...
that work.
2022-03-29 10:17:12 +00:00
Jonathan Woodruff
163ca1d099
Use only parameters that improve performance.
2022-03-25 14:08:43 +00:00
Jonathan Woodruff
9bfaf4cbf0
Swap poliarity of prediction for comparison with upstream.
2022-03-25 14:03:06 +00:00
Jonathan Woodruff
6d7f95571f
Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction
2022-03-25 13:06:22 +00:00
Jonathan Woodruff
ad7bcbb559
Temprarily remove all protections for a baseline bitfile.
2022-03-25 11:09:32 +00:00
Jonathan Woodruff
3248e42485
Temporarily turn off late push so we can run benchmarks for non-push
...
case.
2022-03-21 10:14:08 +00:00
Jonathan Woodruff
3cdc2d31c8
Experimentally increase delay before reset.
2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8
Reset counter if head becomes valid.
2022-03-16 11:39:57 +00:00
Peter Rugg
d0c1d97a2a
Print RVFI packets in RVFI_DII also
2022-03-15 10:04:18 +00:00
Jonathan Woodruff
7b78c0ed7b
Delay returns (up to 10 cycles) if there is an outstanding push.
2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1
Clean up prints
2022-03-11 10:24:39 +00:00
Jonathan Woodruff
37a7745f1a
Fix a few errors in the previous commit, and importantly, make the
...
"push" from writeback just a write to the location that was meant to
push to, rather than the current head.
2022-03-10 11:04:54 +00:00
Peter Rugg
00c0021479
Enable RVFI by default for bluesim builds
2022-03-09 22:18:08 +00:00
Peter Rugg
d005d4ea61
Bump BSV-RVFI-DII
2022-03-09 22:18:08 +00:00
Peter Rugg
a6976c0071
Fix RVFI-only build
2022-03-09 22:18:08 +00:00
Jonathan Woodruff
9d68d877d9
Move to much simpler design.
...
Just update the head in Decode, and write data from Execute.
A loop calling from the same place will at least find the correct
address.
Also, the bad fixup interaction is solved.
2022-03-09 12:32:01 +00:00
Jonathan Woodruff
bbdcf6dde9
A more sophisticated RAS protection delay.
...
Saturate down, and also predict with old push value if there is more
than 6 cycles of delay.
2022-03-08 15:17:54 +00:00
Jonathan Woodruff
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop
...
while waiting for a push.
2022-03-07 17:52:11 +00:00
Franz Fuchs
56c0ca328b
Added missing update due to changing version of BlueStuff
2022-02-28 13:03:00 +00:00
Jonathan Woodruff
6d65de5c88
Experimentally remove delayed RSB_PUSH for synthesis.
2022-02-24 11:49:35 +00:00
Jonathan Woodruff
6ea972931d
Add missing verilog file that is inadvertantly used.
2022-02-23 16:46:43 +00:00
Jonathan Woodruff
28646b252d
Add BSC protections to the hardware makefile.
2022-02-23 11:43:41 +00:00
Jonathan Woodruff
c17874bdba
Add options to disable each of 5 aspects of enforcment of the Branching
...
Speculation Contract.
2022-02-22 16:21:53 +00:00
Franz Fuchs
90f236aab1
Bumped BlueStuff, TagController and BSV-RVFI-DII
2022-02-21 14:39:44 +00:00
Franz Fuchs
f46b961674
Bumped TagController
2022-02-21 09:19:25 +00:00
Jonathan Woodruff
e889bb95fa
Add a "delay" for fixups after a push.
...
A push updates the head pointer from Execute, but the instructions
between Decode and execute will have an out-of-date head pointer.
If a branch in that window mispredicts, it will get the head pointer
out of sync by resetting it to ignore the push.
By delaying by one branch, we seem to eliminate over 60% of the misses,
and reduce the cycle overhead from 0.5% to 0.2% in CoreMark, and still
well ahead of the baseline with no fixup.
2022-02-18 18:00:02 +00:00
Jonathan Woodruff
75d1afe8b4
Only push to RAS when the linking instruction is non-speculative.
...
That is, don't push in Decode, push from the training structure coming
from Execute, which is delayed until the instruction that issued it is
non-speculative.
2022-02-18 13:22:02 +00:00
Jonathan Woodruff
2b9ebb5b40
Ugly hack to avoid redirection epoch from being killed by the killAll.
...
Commit stage redirections are post-prediction and should need to somehow
be treated specially in the SpecFifo for epochs in the fetch stage.
They are post-commit, so should be unkillable somehow. I guess
SpecFifos are not meant to hold post-commit state currently.
2022-02-16 12:23:05 +00:00
Jonathan Woodruff
4961d321b9
Merge branch 'CHERI' into jdw57_prediction
2022-02-16 10:10:00 +00:00
Jonathan Woodruff
e118e7c0ee
Merge branch 'CHERI' into jdw57_schedule_experiments_III
2022-02-14 16:01:47 +00:00
Jonathan Woodruff
05df76073b
Revert some unintended changes from the last commit.
2022-02-01 11:08:37 +00:00
Jonathan Woodruff
01132d165a
Enable tracing of physical addresses for RVFI (if PADDR_RVFI is
...
defined).
This is done by adding a vector of padder lookup interfaces to the load
store queue.
This should help with targeted memory translation debugging, and also
with compatability with the current Sail RVFI implemenation which is
probably incorrect with respect to the RVFI spec which calls for virtual
addresses in the maddr field.
2022-02-01 09:10:48 +00:00
Jonathan Woodruff
ad5d5aca0d
Also pause branch execution when there is a pending wrong speculation.
2022-01-31 12:36:17 +00:00
Jonathan Woodruff
a56deab46c
Simpelest strategy for making wrongSpec not conflict with loads of
...
rules.
This triggers some assertions in the ROB what should be dealt with
properly if this is going to work.
2022-01-31 12:36:17 +00:00
