Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
1,055 Commits 7 Branches 0 Tags
2d05514b669be2be2b3bfa5b805cac4d0bca201b
Commit Graph

1055 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
17a7a32092 Use DRegOR instead of immitating latching behaviour. 2020-12-15 16:18:36 +00:00
jon
d64df09d82 Bump to version with DRegOR. 2020-12-15 16:18:18 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
jon
982758cae7 Bump to version of Bluestuff that has the saturating truncate function. 2020-12-14 12:13:34 +00:00
Jessica Clarke
f6569e2d14 Actually do the intended fix, not just inverting the variable 2020-12-14 10:51:57 +00:00
Jessica Clarke
295b878836 Fix negated CYCLE/INSTRET logic for ASR and make less confusing 2020-12-14 10:50:23 +00:00
jon
6768bf92c7 iMove the store count to the pipeline write. 
It appeared to be counting capabilities in store counter flushes, which,
FI think, is not quite what was intended in this counter.
 2020-12-11 17:16:38 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
bdc2d494f2 Change name something that makes sense. 2020-12-04 17:12:26 +00:00
jon
3f60c046f7 Fix typo. 2020-12-04 16:51:44 +00:00
jon
f42c3f3577 Merge branch 'cheri-perfmon' into CHERI 2020-12-04 16:29:51 +00:00
jon
5665d2e9cd A more effective Fence count (as some fences go through as the Nop 
iType).
 2020-12-04 16:28:19 +00:00
jon
425c2778c0 Bump Bluestuff to get resetting in the Performance Monitor. 2020-12-03 17:55:03 +00:00
jon
1fb388fb18 Count more things correctly. 2020-12-03 17:54:46 +00:00
jon
8a13b866d7 Bump bluestuff to the one with generalised report width. 2020-12-02 15:31:49 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
742c4c5c92 Bump Bluestuff. 2020-12-01 18:03:44 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00
Nathaniel Filardo
6e4c378d4d CHERI ISAv8 CapDirty fault priority fix 
Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
 2020-11-06 19:15:47 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Peter Rugg
bf77ac74ba Fix performance reporting requests for multicore 2020-11-04 12:11:31 +00:00
Peter Rugg
61b88ef987 Generate elf files the correct size 2020-11-02 11:23:07 +00:00
Marno van der Maas
328592b068 Added missing slash in readme 2020-10-29 15:45:17 +00:00
Jonathan Woodruff
29168574ca Revert "Sort of support 2 cores for starting and halting." 
This reverts commit b4b7718aa2.
 2020-10-16 15:44:53 +01:00
jon
b4b7718aa2 Sort of support 2 cores for starting and halting. 2020-10-08 15:09:23 +01:00
PeterRugg
844bfd5e79 Merge pull request #5 from nwf/capdirty 
Add CHERI PTE CapDirty flag
 2020-10-02 17:17:24 +01:00
Marno van der Maas
ed9541e8d0 Put all dirs for source description in code blocks 2020-10-02 13:09:51 +01:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00
jon
9508eada79 Change to allow 1-way superscalar to build without error. 2020-09-17 14:40:46 +01:00
jon
1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. 
(Previously we ran into the limit of ports on the regFiles holding state
in the BTB.  This uses a vector of regFiles with a vector of interfaces,
which is logically the same but might produce multiple copies of state.)
 2020-09-16 11:42:19 +01:00
jon
96afb0a7f5 FIFO optimisation both for build time (and possibly condition 
complexity?) and for throughput.
 2020-08-13 17:33:46 +01:00
jon
4c74d27e4e Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:31:30 +01:00
jon
7a93056b8b Increase the capacity of f32d to enable full throughput. 
I don't know why this is necessary, but this allows performance parity
with the baseline.
 2020-08-11 15:30:03 +01:00
jon
9230fcc3b4 Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:25:12 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
jon
3b97fbe255 Rename last->prev for clarity. 2020-07-31 13:46:33 +01:00
jon
f63673c3f3 First working implementation of the new instruction picker. 
Evidence of "working" is passing TestRIG to a cursory depth including
compressed instructions and running CoreMark in simulation.
This one appears to be 2.5% slower than the existing design in CoreMark,
so some optimisation should be done.  We expect it to be a bit faster
than the original due to more flexibility in decoding instructions from
different fetch units together.
 2020-07-31 11:25:28 +01:00
jon
3a9e76c1fd Fix bug where the wrong bounds were attached to a mispredicted half of 
an instruction.
 2020-07-29 12:32:28 +01:00
jon
8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." 
This reverts commit 4fe24c9cd5.
 2020-07-29 11:40:00 +01:00
jon
4fe24c9cd5 Remove the special flush from the Fetch3 stage. 
This is an intermediate simplification for moving to SupFifo-based picking.
 2020-07-29 07:40:15 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00
Jessica Clarke
73dedec309 FetchStage: Use map rather than for loop 
Also add some spaces in the following line.
 2020-07-24 20:02:10 +01:00
Jessica Clarke
0b3ad23c24 Fix typo 2020-07-24 19:10:11 +01:00