Jonathan Woodruff
6d7f95571f
Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction
2022-03-25 13:06:22 +00:00
Jonathan Woodruff
3cdc2d31c8
Experimentally increase delay before reset.
2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8
Reset counter if head becomes valid.
2022-03-16 11:39:57 +00:00
Jonathan Woodruff
7b78c0ed7b
Delay returns (up to 10 cycles) if there is an outstanding push.
2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1
Clean up prints
2022-03-11 10:24:39 +00:00
Jonathan Woodruff
37a7745f1a
Fix a few errors in the previous commit, and importantly, make the
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"push" from writeback just a write to the location that was meant to
push to, rather than the current head.
2022-03-10 11:04:54 +00:00
Peter Rugg
a6976c0071
Fix RVFI-only build
2022-03-09 22:18:08 +00:00
Jonathan Woodruff
9d68d877d9
Move to much simpler design.
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Just update the head in Decode, and write data from Execute.
A loop calling from the same place will at least find the correct
address.
Also, the bad fixup interaction is solved.
2022-03-09 12:32:01 +00:00
Jonathan Woodruff
bbdcf6dde9
A more sophisticated RAS protection delay.
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Saturate down, and also predict with old push value if there is more
than 6 cycles of delay.
2022-03-08 15:17:54 +00:00
Jonathan Woodruff
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop
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while waiting for a push.
2022-03-07 17:52:11 +00:00
Jonathan Woodruff
75d1afe8b4
Only push to RAS when the linking instruction is non-speculative.
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That is, don't push in Decode, push from the training structure coming
from Execute, which is delayed until the instruction that issued it is
non-speculative.
2022-02-18 13:22:02 +00:00
Jonathan Woodruff
4961d321b9
Merge branch 'CHERI' into jdw57_prediction
2022-02-16 10:10:00 +00:00
Jonathan Woodruff
05df76073b
Revert some unintended changes from the last commit.
2022-02-01 11:08:37 +00:00
Jonathan Woodruff
01132d165a
Enable tracing of physical addresses for RVFI (if PADDR_RVFI is
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defined).
This is done by adding a vector of padder lookup interfaces to the load
store queue.
This should help with targeted memory translation debugging, and also
with compatability with the current Sail RVFI implemenation which is
probably incorrect with respect to the RVFI spec which calls for virtual
addresses in the maddr field.
2022-02-01 09:10:48 +00:00
Jonathan Woodruff
ad5d5aca0d
Also pause branch execution when there is a pending wrong speculation.
2022-01-31 12:36:17 +00:00
Jonathan Woodruff
a56deab46c
Simpelest strategy for making wrongSpec not conflict with loads of
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rules.
This triggers some assertions in the ROB what should be dealt with
properly if this is going to work.
2022-01-31 12:36:17 +00:00
Jonathan Woodruff
4fbb7b5648
A version that seems to actually run.
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The buffer in GlobalSpecUpdate has to be a SpecFifo.
2022-01-31 12:09:38 +00:00
Jonathan Woodruff
c1c4a46b1e
Simpelest strategy for making wrongSpec not conflict with loads of
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rules.
This triggers some assertions in the ROB what should be dealt with
properly if this is going to work.
2022-01-31 12:09:38 +00:00
Jonathan Woodruff
4cfd652b0d
Use mkRegOR in register file.
2022-01-25 20:42:16 +00:00
Jonathan Woodruff
e497091e18
A timing optimisation for the direction predictor.
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Add a "nextPc" interface so that lookup can begin in the previous cycle.
Remove the "pc" operands in the vector of lookup interfaces,
but rather derive the PC from lookup from the first PC being looked up
in that cycle. That is, by adding 4*(interface number) to the beginning
lookup PC. As this might not actually be the PC of the instruction,
pass the index you used with the training info so that you are certain
to train with the same index you looked up.
This has less than 1% overhead in CoreMark.
This is a general improvement for reasonable timing which should be upstreamed.
2022-01-18 11:05:09 +00:00
Jonathan Woodruff
1f8181d595
Move to (recently merged) non-pipelined Divide.
2022-01-13 11:14:20 +00:00
Jonathan Woodruff
37f6dbde93
Timing optimisation for Tournament Predictor.
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Start global-history-indexed lookups in the previous cycle.
This is a general timing optimisation that should be pushed upstream at
some point.
2022-01-12 16:08:33 +00:00
Jonathan Woodruff
e600fd7d38
Delay BTB update by a cycle for timing.
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This should not be a primary degredation of performance since the
redirection gets on seperately from this update which will only affect
future predictions.
2022-01-08 10:16:50 +00:00
Jonathan Woodruff
b84562a027
Improve scheduling for LatencyTimer to improve timing path discovered on
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DE10.
2022-01-07 09:52:43 +00:00
Jonathan Woodruff
f619f4b0a1
Make the associative BTB compressed.
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That is, only store the bottom 16 bits of the target if the upper bits
of pc and nextPc match.
Have a single "way" dedicated to full targets.
2021-12-20 17:24:55 +00:00
Jonathan Woodruff
54d1a204f0
Don't decode redirected streams until they are non-speculative.
2021-12-17 16:29:14 +00:00
Jonathan Woodruff
4cc86b1e56
Revert more changes to buffer speculative training, as previous
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buffering of training from execute should be sufficient for the BTB as
well.
2021-12-16 15:01:46 +00:00
Jonathan Woodruff
3322d1d3d7
Revert "An attempt at wiring up the specUpdate interface for the Btb."
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This reverts commit 022df36199 .
2021-12-16 12:10:50 +00:00
Jonathan Woodruff
022df36199
An attempt at wiring up the specUpdate interface for the Btb.
2021-12-15 18:40:58 +00:00
Jonathan Woodruff
696f546ecb
Version using searchableSpecFifo in BTB with actual searching, but
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without killing speculative elements yet. This one is full performance
in CoreMark.
2021-12-15 18:27:45 +00:00
Jonathan Woodruff
657453a0a0
Two modules (that build) that should be helpful in delaying the commit
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of training data.
2021-12-15 17:06:46 +00:00
Jonathan Woodruff
af69f2e5db
Merge branch 'CHERI' into jdw57_prediction
2021-12-15 16:47:42 +00:00
Jonathan Woodruff
34c6ee1894
Specifically give priority to wrong_spec when they conflict.
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This appears to yield 10% performance improvement as our default setup
appears to choose a wrong priority.
2021-12-03 12:36:40 +00:00
Franz Fuchs
37074525e1
removed unnecessary execute permissions for Decode.bsv, Exec.bsv, ProcTypes.bsv, ReorderBuffer.bsv, and AluExePipeline.bsv
2021-11-29 10:38:23 +00:00
Jonathan Woodruff
59836cc9e5
Hopefully optimise this function to have just one call to modifyOffset.
2021-11-26 11:07:12 +00:00
Jonathan Woodruff
ad149db5c0
Hopefully optimise this function to have just one call to modifyOffset.
2021-11-25 17:39:46 +00:00
Jonathan Woodruff
cc0114f645
Swap write priority, as suggested by Franz.
2021-11-16 15:40:01 +00:00
Jonathan Woodruff
7b472d4d3c
Reduce area overhead by using an unguarded specfifo that does not have
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to be worst-case-sized, but can drop elements if it is full.
2021-11-16 13:53:34 +00:00
Jonathan Woodruff
618dea1225
Feed head of RAS through to execute with training info to reset the head
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on a misprediction.
2021-11-16 11:00:04 +00:00
Jonathan Woodruff
d56045effe
Make the associative BTB compressed.
...
That is, only store the bottom 16 bits of the target if the upper bits
of pc and nextPc match.
Have a single "way" dedicated to full targets.
2021-11-15 11:50:57 +00:00
Marno
0f86f09b6a
Updated copyright statement
2021-11-11 12:15:45 +00:00
Marno
6ae92f786b
Checking tag and seal on rVal2 and checking type on rVal1 in a way that does not use undefined behavior.
2021-11-11 11:36:45 +00:00
Marno
4d1dc29f79
Added ccopytype_bypass
2021-11-10 11:53:26 +00:00
Jonathan Woodruff
04a5d82ff0
Go back to standard tournament predictor (which performs the best on
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CoreMark), though cleaning up slightly to use standard functions.
2021-11-10 09:54:34 +00:00
Jonathan Woodruff
8379d77cc5
Don't use a synthesis barrier for Bht so that we don't have to add it to
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XML. The direction predictor already has one anyway.
2021-11-08 13:51:52 +00:00
Jonathan Woodruff
e342600cb5
Try the traditional Bht, as it seems like it might be less fiddly with
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speculative training.
2021-11-08 12:34:07 +00:00
Jonathan Woodruff
6713505d12
Experiment with different Bht constants to see if these affect our
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benchmark.
2021-11-05 18:52:40 +00:00
Jonathan Woodruff
d5e52a9ecb
Revert to upstream direction predictors to reduce diffs and prepare for
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improvements that can be upstreamed.
Basically, only use addresses in these predictors rather than
capabilities, and just pass an address in from the FetchStage.
2021-11-05 17:42:19 +00:00
Jonathan Woodruff
836ed5b143
Merge branch 'jdw57-jr-bsc-safety' into CHERI
2021-11-03 16:46:21 +00:00
Jonathan Woodruff
3908c5f955
A merge resolution not included in previous commit due to not saving file.
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Doh.
2021-11-02 18:12:05 +00:00