This includes replacing register read values with nullCap if reading x0, which is generally necessary.
This is more-or-less using a new mechanism which shouldn't actually be necessary if the default value in the register file is nullCap.
(In RVFI_DII, we initialise with the almightyCap instead.)
This required makeing the Exception type wider by one.
The actual "inBounds" check is currently implemented in the reorder buffer rows, which duplicates the logic ~80 times (number of outstanding instructions), which isn't ideal, but it's using the quick in-bounds check that only compares the mantissa-sized things.
Also move to SetAddrUnsafe, as is traditional for setting the address of PCC where we do proper checks on branches so we really only have the possibility of executing off the end of the length, and therefore cannot become unrepresentable.
This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty". Tandem Verification
trace-generation was not reporting this update.
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response. Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
src_Core/CPU/CsrFile.bsv
Various fixes for WARL'd values of mstatus and sstatus, medeleg,
Added tval field in Trap_Updates returned by csrf.trap
src_Core/Core/Trace_Data2.bsv
Added fields for store_data and store_data_BE
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
Added treatment of store_data and store_data_BE
Fixed bug in next_pc for mkTrace_RET
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Fixed Trace_Data2 struct to TV for pc in case of xRET, and tval in case of trap
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
Added store_data and store_data_BE in calls to rob_setExecuted_doFinishMem
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Added store_data and store_data_BE in methods rob_setExecuted_doFinishMem
Now handling all Alu and Fpu pipeline outputs, traps and xRets.
Still todo:
(1) Mem pipeline outputs (Ld, Lr/Sc, Amo outputs to dest reg)
(2) For CSRRx, currently reporting WARL pre-write updates; needs to be WARL'd update.
Rd value (destination register) of Integer ops supported
Trap updates (priv and CSR updates) supported.
Still pending: Memory ops Rd value, Fpu Rd value
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
- dm_reset, hart_reset, ndm_reset
- break (set breakpoint)
- step
- continue (until breakpoint of 'halt' command)
- halt
- read/write GPR, FPR, CSR, memory
- elf_load
When controlled from a debugger (build with INCLUDE_GDB_CONTROL macro);
when stopped due a EBREAK instruction; on a 'resume' command ('continue' in GDB),
was getting stuck. This is now working.
At this point, all debugger functionality (almost: see below) is working:
halt, step, breakpoints, resume, read/write gpr/fpr/csr, read/write memory.
Still todo: "NDM reset" (non-debug module reset).
This is not thoroughly tested, as we quickly throw an exception due to out-of-bounds memory and need some RVFI-DII control flow fixup to proceed further.
This stopped unmapped addresses from faulting, instead giving back a
list of all Invalid entries, triggering the "Fetched insts not enough"
assertion in FetchStage's doDecode. Fixes rv64mi-p-access.
