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7618c5cec8ff9727e0697313be8e865582dc3c3f
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Author SHA1 Message Date
jon
7618c5cec8 Trap on access of fcsr when floating point is not enabled. 2020-04-02 13:05:42 +01:00
jon
4714070aef Trace the next PC correctly for mret. 2020-04-01 18:43:48 +01:00
jon
c2917d558f Bump library version to that required by current design. 2020-04-01 14:44:21 +01:00
Peter Rugg
fe2420e42f Allow running isa_tests on CPUs with <=4 cores 2020-03-31 17:34:41 +01:00
Jonathan Woodruff
81da99237e Move the register file to CapReg format, and pipe CapPipe around the pipeline. 2020-03-31 15:44:23 +01:00
Jonathan Woodruff
0580a24b86 Bump library to version including new casts needed for recent changes. 2020-03-31 15:43:14 +01:00
Jonathan Woodruff
480b5923da Make type of register file generic. 2020-03-30 15:20:28 +01:00
Jonathan Woodruff
dbcc4a6c22 Re-add dummy Mem.hex file. 2020-03-30 15:18:01 +01:00
Jonathan Woodruff
db41e2b9ed An initial implementation of mccsr. 2020-03-27 17:47:02 +00:00
Alexandre Joannou
b5b2b4fe5c Port AXI4 changes from Flute 2020-03-27 16:45:26 +00:00
Alexandre Joannou
92815e957e Add BlueStuff to Makefile 2020-03-27 16:45:24 +00:00
Jonathan Woodruff
ded8dc72e7 Do the MTCC->PCC->MEPCC shuffle on trap. 2020-03-27 15:55:02 +00:00
Jonathan Woodruff
8d61c8db73 Remove unnecessary copy of submodule. 2020-03-27 15:54:06 +00:00
Jonathan Woodruff
c035f359e8 Merge branch 'CHERI' into pdr32-tmp 
and get it to build!
 2020-03-26 18:03:58 +00:00
Peter Rugg
5f33b1c87a Very initial decode and ALU work for CHERI 2020-03-26 14:35:02 +00:00
Jonathan Woodruff
d5b73a2d50 Add DDC exception. 
Also enable working exception reporting for the memory pipe.
 2020-03-26 14:29:06 +00:00
Jonathan Woodruff
f2f2285f75 Check the bounds on PCC and report the correct exception in Xcause registers. 
This required makeing the Exception type wider by one.
The actual "inBounds" check is currently implemented in the reorder buffer rows, which duplicates the logic ~80 times (number of outstanding instructions), which isn't ideal, but it's using the quick in-bounds check that only compares the mantissa-sized things.
 2020-03-25 15:20:03 +00:00
Jonathan Woodruff
88ca03f4ed Pipe through an exception to the Reorder buffer from each execute pipe. 
Also move to SetAddrUnsafe, as is traditional for setting the address of PCC where we do proper checks on branches so we really only have the possibility of executing off the end of the length, and therefore cannot become unrepresentable.
 2020-03-25 11:51:33 +00:00
Jonathan Woodruff
c813abe9c9 Write pcc bounds into reorderbuffer pc in the all execute pipeline stages. 
This allows pcc bounds to be consistent in the model of CSRs (written in commit and read in execute) in preparation for fancier forwarding eventually.
 2020-03-25 09:10:38 +00:00
Jonathan Woodruff
22938d2384 Propagate a CapPipe through the PC of each instruction record. 2020-03-23 17:24:05 +00:00
Jonathan Woodruff
2aa902f61a Change tabs to 8 spaces, this time being careful to do this only in BSV files. 2020-03-23 14:44:39 +00:00
Jonathan Woodruff
a6e5a7bff0 Revert "Fix whitespace in src_Core directory." 
This reverts commit a137a6ede7.
 2020-03-23 14:40:02 +00:00
Jonathan Woodruff
a137a6ede7 Fix whitespace in src_Core directory. 
Replace all tabs with 8 spaces.
 2020-03-23 14:28:00 +00:00
Jonathan Woodruff
43fa43e2c9 Implement writes to PCC and preparation for checking the bounds of PCC. 2020-03-23 14:24:44 +00:00
Jonathan Woodruff
a299a763ed Add a special capability register file and pass it's interfaces to all the places that the current CSR file goes. 
We may need to trim some of these later, but most of them seem like places that we'll need access.
 2020-03-23 10:10:11 +00:00
Jonathan Woodruff
c97ee15851 A couple initial files with beginnings of CHERI support. 2020-03-20 15:34:18 +00:00
Jonathan Woodruff
c5378a7a99 Merge branch 'RVFI_DII' into CHERI 2020-03-20 11:41:15 +00:00
Jonathan Woodruff
796e3a645d Bump to version that imports string.h. 2020-03-20 11:40:10 +00:00
Jonathan Woodruff
d77c158b76 Merge branch 'mac_build' into RVFI_DII 2020-03-20 11:35:11 +00:00
Jonathan Woodruff
b830f4bf41 Resolve some issues to build on mac. 
This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
 2020-03-19 19:21:59 +00:00
Alexandre Joannou
f9657e1222 Merge branch 'RVFI_DII' into CHERI 2020-03-18 13:05:53 +00:00
Jonathan Woodruff
3a79b022ea Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage! 2020-03-18 11:35:59 +00:00
Peter Rugg
70ede793d6 Add CHERI subrepos 2020-03-16 15:44:17 +00:00
Jonathan Woodruff
1246aae7f8 Commented back in necessary PC update. 2020-03-13 13:11:07 +00:00
rsnikhil
c278e4fe68 Fixed a bug, and a related Tandem-Verification bug, re. CSR MIP MEIP/MTIP/MSIP. 
Two of these were not properly restricted as read-only from CSRRX instructions,
and there was a bug in the WARL function for writing MIP,
and there was a bug in the TV-reporting of MIP updates.
 2020-03-12 21:44:00 -04:00
Jonathan Woodruff
264f99f06b Track the next PC accurately. 2020-03-12 18:17:45 +00:00
Jonathan Woodruff
72de623779 Add dummy hex file. 2020-03-12 15:15:17 +00:00
Jonathan Woodruff
f0bfea4590 Bump submodule. 2020-03-12 12:24:13 +00:00
Jonathan Woodruff
5851d254ad Add a needed verilog file. 2020-03-12 11:48:09 +00:00
Jonathan Woodruff
0d525e4d11 Add RVFI_DII build Makefile. 2020-03-12 11:18:44 +00:00
Jonathan Woodruff
b24b6ab109 Bump the RVFI_DII library. 2020-03-12 10:47:30 +00:00
Jonathan Woodruff
79935d848f Reduce "verbosity". 2020-03-12 10:47:07 +00:00
Jonathan Woodruff
41fd6b2b60 Updated conditions to print the destination register and value correctly for various instruction types. 2020-03-12 10:46:00 +00:00
Jonathan Woodruff
a7a2854888 Declarations required for updated socket library. 2020-03-12 10:45:34 +00:00
rsnikhil
f02e9af515 Improved avoidance of initial timer interrupt in MMIOPlatform; removed spurios MSTATUS TV report on CSRRS/C with rs1==0 2020-03-11 22:42:18 -04:00
Jonathan Woodruff
3eccf92544 Move to 8 MiB RVFI-DII memory. 2020-03-11 11:53:19 +00:00
rsnikhil
a19eb97f34 Small tweak to MMIOPlatform.bsv to avoid spurious timer interrupt at start of time. 2020-03-09 22:58:04 -04:00
rsnikhil
b00f1d2eec Fixed a Tandem Verification trace generation bug for FMV.X.F and FMV.X.D 
We were reporting the incremental value of fflags (=0)
instead of the final value of fflags (same as pre-value, which may not be 0).
 2020-03-09 14:47:20 -04:00
rsnikhil
976494a8ff Fixed Tandem-Verification trace generation issue re. MSTATUS on CSRRx instructions that write to FCSR. 
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty".  Tandem Verification
trace-generation was not reporting this update.
 2020-03-08 21:29:30 -04:00
rsnikhil
fafd99c983 Fixes reported by Joe Stoy: PLIC, MMIO_AXI4_Adapter and Core.bsv (details below) 
PLIC: updated to latest version from Piccolo/Flute.

MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
    AXI4 fabrics. Writes that specify 8-byte size, but only write in
    upper or lower word using strobes, are converted into 4-byte size.

Core.bsv: added a notification to the Debug Module re. CPU halt.
 2020-03-08 15:39:57 -04:00