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Author SHA1 Message Date
Jonathan Woodruff
854e8e5bfb Another experiment to see if we can resolve the vcu118 build. 
This one puts the in-order shim before the width converter.
 2024-04-05 10:54:39 +01:00
Jonathan Woodruff
8990ae56ed Revert "Potential workaround for issue with vcu118 memory bus error." 
This reverts commit f86ea0203d.
 2024-04-05 10:44:50 +01:00
Jonathan Woodruff
f86ea0203d Potential workaround for issue with vcu118 memory bus error. 
Just use the same ID for all outstanding requests such that all requests
are in-order.
Previously we were working fine with requests serialised; requests
are now fully pipelined and out-of-order.
This change should roll back to in-order, but still pipelined.
This only affects the top-level used in the GFE (vcu118).
This design is working on the DE10 setup, so the issue is not
believed fundamental with CoreW.
 2024-04-04 14:09:16 +01:00
Jonathan Woodruff
6f8c371a5c Roll back DTlB to two cycles for timing on DE10. 2024-03-25 12:52:51 +00:00
Jonathan Woodruff
e0eefbcfd0 Be a little more careful with outstanding requests. 2024-03-18 09:10:55 +00:00
Jonathan Woodruff
235f025db8 Bump Bluestuff. 2024-02-20 14:19:46 +00:00
Peter Rugg
dd076fb189 Bump BlueStuff 2024-02-16 17:04:13 +00:00
Jonathan Woodruff
271bc9c0e8 Experimentally remove deburster. 
This thing has a seraliser in it that serialises memory accesses, which
is a disaster for performance.
 2024-02-16 09:50:07 +00:00
Jonathan Woodruff
6838b02274 Move to 4-way L1 caches to reduce area usage of splitting data ways into 
seperate BRAMs.
 2024-02-05 09:40:15 +00:00
Jonathan Woodruff
0784902e45 Tune the instruction fetch FIFO to the lower-latency ICache. 2024-02-02 13:26:15 +00:00
Jonathan Woodruff
b65994c00c Include the new single-cycle CCPipe as a seperate implementation, and 
use it only in the L1 caches so that the L2 cache can have lower
resource utilisation and better timing.  (Resource utilisation is up
about 5% with the new design, and it's not necessary for the L2 cache.)
 2024-02-02 11:50:45 +00:00
Jonathan Woodruff
ccc71952bf Use forwarding BRAMs in L2 Cache. Duh; this is required for the new 
CCPipe structure.
 2024-02-01 13:44:36 +00:00
Jonathan Woodruff
7608543da5 Move back to more traditional implementation of the forwarded BRAM, 
which also workst.
 2024-02-01 10:07:48 +00:00
Jonathan Woodruff
3416040a74 Forward using a working forwarding memory rather than logic in CCPipe. 
This design runs CoreMark successfully.
 2024-01-31 13:29:59 +00:00
Jonathan Woodruff
0e87595d73 Work toward eliminating a cycle of cache latency by doing data lookup in 
parallel with tag lookup.
 2024-01-31 10:15:51 +00:00
Jonathan Woodruff
8e4848c4bc Turn off tracing in instruction fetch. 2024-01-26 16:32:16 +00:00
Jonathan Woodruff
be26ac9f79 Fix a typo in a comment. 2024-01-26 16:31:49 +00:00
Jonathan Woodruff
9baadf58f3 Tune the size of the fetch pipeline fifos. This appears to make a 3% 
performance improvement in CoreMark.
 2024-01-26 16:02:18 +00:00
Jonathan Woodruff
e873bbd553 Clean up Fetch stage optimisations. This includes removing references 
to Fetch3, which no longer exists since Fetch2 and Fetch1 are merged
(Fetch3 is now Fetch2).
 2024-01-26 15:14:03 +00:00
Jonathan Woodruff
ca4e120a6c Use DReg instead of Reg, as intended. 2024-01-22 12:06:39 +00:00
Jonathan Woodruff
b586937953 Fix RVFI_DII by only going to the next ID when the instruction fetch is 
going ahead.
 2024-01-22 11:38:52 +00:00
Jonathan Woodruff
640f330d7d Briefly report flush when vm_info has a change in the itlb to give an 
opportunity to flush the buffered translations.
 2024-01-19 11:48:04 +00:00
Jonathan Woodruff
d30bd71e72 Allow consuming TLB response while TLB is being flushed. 2024-01-18 13:04:21 +00:00
Jonathan Woodruff
83c756a4f4 Tidy up data mem pipeline changes to remove duplicated code. 2024-01-17 16:09:42 +00:00
Jonathan Woodruff
9d12fefda8 Remove commented-out code. 2024-01-17 14:30:34 +00:00
Jonathan Woodruff
829a787be5 Move to vector functions as it's cleaner. 2024-01-17 13:41:43 +00:00
Jonathan Woodruff
5a1ed7c57f Allow a vector of translations to be remembered. 
Just do 2 for now.
 2024-01-17 13:21:38 +00:00
Jonathan Woodruff
4f91e54bd2 Properly remove pipline stage in fetch and use a seperate rule to do the 
proper TLB lookup if necessary.
 2024-01-16 17:00:10 +00:00
Jonathan Woodruff
eee5a2c23b Experiment with a zero-cycle TLB in instruction fetch as well. 2024-01-16 10:05:17 +00:00
Jonathan Woodruff
25a728b6d3 Optimise timing of TLB translation, ensuring that the translated address 
proceeds with minimal conditions to the output.
 2024-01-16 09:50:35 +00:00
Jonathan Woodruff
f9bf4ad856 Use default value on reset of Map. 2024-01-15 17:00:00 +00:00
Jonathan Woodruff
2c3c1da5c3 Solve last issue to allow doExeMem and doFinishMem. 2024-01-09 17:12:39 +00:00
Jonathan Woodruff
2f6a0980d9 Move all the work other than the TLB request out of doExeMem back to 
doRegReadMem.
 2024-01-09 12:37:34 +00:00
Jonathan Woodruff
3e3531ffd5 Revert "A scheduling experiment to try to get doRegReadMem and doExeMem" 
This reverts commit b733e05a86.
 2024-01-09 11:54:53 +00:00
Jonathan Woodruff
b733e05a86 A scheduling experiment to try to get doRegReadMem and doExeMem 
executing in the same clock cycle.  It doesn't seem to work (yet).
 2024-01-09 11:52:29 +00:00
Jonathan Woodruff
32d094082b Some tracing for performance in the memory pipeline. 
Also, add some ports to registers in DTLB to potentially allow
single-cycle lookup.
 2024-01-08 15:28:24 +00:00
Jonathan Woodruff
2d05514b66 An experimental simplification of the SplitLSQ, which I think works 
because the Memory pipeline only ever reads the getIssueLd interface in
the same rule that it calls issueLd.
 2023-12-12 17:29:27 +00:00
Peter Rugg
8cd6e8db87 Bump BlueStuff 
This includes the changes to add wrappers for the delay shim. Unfortunately,
these are not directly suitable for the VCU118 setup since the uncached bus
needs to configure either itself or the cached bus, so leave those as is for
now
 2023-10-31 13:28:00 +00:00
gameboo
9dae87b505 Bump cheri-cap-lib 2023-10-31 13:28:00 +00:00
Peter Rugg
e9c2db4e60 Allocate mem_buf dynamically in elf_to_hex 
This hopefully fixes various compile issues due to having a > 2GB global
and also seems to have the size effect of running many times quicker.
 2023-10-25 13:35:32 +01:00
Simon Moore
d04c8ea3a9 Tidy section formatting so that it better exports to asciidoctor. 2023-08-30 18:26:47 +01:00
gameboo
da473192c7 Bump BlueStuff 2023-08-24 17:18:00 +01:00
gameboo
5ca4843be1 Bump BlueStuff 2023-08-21 14:30:26 +01:00
Peter Rugg
16592ae29a Bump BlueStuff 2023-08-16 18:30:27 +01:00
gameboo
43378ee339 Bump BlueStuff 2023-07-25 16:05:15 +01:00
Peter Rugg
4acbe2f43b Fix build error with SPEC contracts 2023-07-17 17:38:57 +01:00
Peter Rugg
5818a886dd Factor out delay shim 2023-07-15 22:37:45 +01:00
Peter Rugg
d509ab0fab Mask off address bits in latency shim 2023-07-15 22:37:45 +01:00
Peter Rugg
5414a13d3b Add prints for latency rules 2023-07-15 22:37:45 +01:00
Peter Rugg
f71f650023 Allow dynamic latency config 2023-07-15 22:37:45 +01:00