Karlis Susters
2c9428d1f3
Prepared repo for building on FPGA
2023-02-13 21:52:50 +00:00
Karlis Susters
9d027a3f4b
Implemented BRAM versions of stride, target, markov prefetchers
2023-02-13 11:59:26 +00:00
Karlis Susters
31ae938e78
Implemented a stride prefetcher with BRAM instead of vectors
2023-02-13 11:59:26 +00:00
Karlis Susters
79c55c5651
Implemented cross cache prefetching, fixed some coherence bugs in LLC
2023-02-13 11:59:26 +00:00
Karlis Susters
dca4b980c5
Implemented a markov chain data prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
9f733eddf1
Merged reportHit & reportMiss, changed compile time parameter passing
2023-02-13 11:59:26 +00:00
Karlis Susters
06e648df6a
Implemented target table module, refactored single and multi window instruction prefetchers to use it
2023-02-13 11:59:26 +00:00
Karlis Susters
7c05ebbd90
Implemented multi line target prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
e602d4780e
LLC prefetcher fixes and single window target prefetcher implementation
2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
Peter Rugg
50c51e93a1
Add assertion that ndm resets don't get dropped
2023-02-09 14:34:13 +00:00
Peter Rugg
6931201a14
Avoid wedge on repeated debug resumes (with jdw57 and aj443)
...
ConfigReg avoids a compile error
2023-01-31 21:02:17 +00:00
Peter Rugg
e120b3427d
Merge branch 'LoadTagsImprove' into CHERI
2022-11-14 13:28:44 +00:00
Alexandre Joannou
54456b5f50
Fix the non-rvfi_dii build
2022-10-21 09:50:49 +00:00
Franz Fuchs
de0e19ca55
added do not cares for missing struct fields in ROB
2022-10-21 09:22:31 +00:00
Jonathan Woodruff
0562cb18a1
Fix for RVFI_DII build.
2022-10-21 09:18:28 +00:00
Alexandre Joannou
02ba37bf6a
Report the actual running state to the debug module
2022-09-08 13:20:35 +00:00
Alexandre Joannou
a0d471e4f8
Attempt to make toHost setiing behave in src_Testbench
...
Made the proc start method non-blocking on mmio platform and wired in a new way
to set the tohost addr using a control and status request, and bumpped
WindCoreInterface accordingly
2022-09-06 10:42:34 +00:00
Alexandre Joannou
d068df3bd8
uncomment a verbosity check
2022-09-02 12:37:07 +00:00
Alexandre Joannou
2240c87c78
Fix src_Testbench toplevel build for tests and bump BlueStuff
2022-08-25 15:25:55 +00:00
Alexandre Joannou
5bf15adf04
Addressed @francislaus comments
2022-08-17 08:41:27 +00:00
Jonathan Woodruff
1fceb8fa72
Use standard imports as the fixes have been upstreamed.
2022-08-15 16:18:23 +00:00
gameboo
6b51139c9a
Update ack
2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b
NonPipelined API update
2022-08-15 16:18:23 +00:00
Alexandre Joannou
f292c5196d
Rename master_xactor to axiShim in DM_System_Bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
47930189da
Bump BlueStuff + assume external subordinate_0 parameters that match internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a
Bump BlueStuff + add outter subordinate trafic as master to internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
bb62b703c8
Address some rebase nonsense
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a65c93ee98
Update resetting in coreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
2c450aea8c
Some reset adjustments
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38
Use NonPipelined dividers + update "reset_by" in CoreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
b32da9034b
Fix addr to DM_addr convertion (pointed out by jrtc27)
2022-08-15 16:18:23 +00:00
gameboo
45135a0bee
Don't assume a XILINX tool flow
2022-08-15 16:18:23 +00:00
gameboo
72320b32b2
Update to AXI lite for debug module port
2022-08-15 16:18:23 +00:00
gameboo
b9ee27f390
Update to WindCoreMid + Bump WindCoreInterface
2022-08-15 16:18:23 +00:00
gameboo
812c961360
Introduce the WindCoreInterface
2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c
Fixes for load address tracing.
2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4
commented out debug print statements in Ras.bsv
2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d
added typedefs to STLPred
2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90
removed unnecessary declarations in RenameStage
2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0
Fix tracing of writes to MMIO addresses.
2022-07-22 15:37:25 +00:00
Franz Fuchs
502e64c24b
fixed not defined warning in ConnectalBramFifo
2022-07-11 15:11:59 +01:00
Franz Fuchs
4abf838d62
implemented missing notFull method in SpecFifo
2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d
used RVFI defines as declared in ToReorderBuffer
2022-07-11 14:18:19 +01:00
Alexandre Joannou
9960d67ed8
Removed some debug print statements
2022-07-11 11:55:40 +00:00
Franz Fuchs
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc
Attempt to clear tag on exception path before forwarding.
...
This is likely to be bad for timing, but might just work at 25MHz.
2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a
corrected ifdef in STLPred.bsv
2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093
added no prediction STL predictor
2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa
added STL predictor module and moved state from SplitLSQ to it
2022-06-08 12:04:25 +01:00
