Cheri-research/Toooba
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Commit Graph

326 Commits

Author SHA1 Message Date
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Jonathan Woodruff
1fceb8fa72 Use standard imports as the fixes have been upstreamed. 2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b NonPipelined API update 2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38 Use NonPipelined dividers + update "reset_by" in CoreW 2022-08-15 16:18:23 +00:00
Franz Fuchs
2f595167a4 commented out debug print statements in Ras.bsv 2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d added typedefs to STLPred 2022-07-26 09:18:20 +01:00
Franz Fuchs
4abf838d62 implemented missing notFull method in SpecFifo 2022-07-11 14:56:30 +01:00
Franz Fuchs
c85b13c5af added MELTDOWN_CF ifdef and enabled it 2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc Attempt to clear tag on exception path before forwarding. 
This is likely to be bad for timing, but might just work at 25MHz.
 2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a corrected ifdef in STLPred.bsv 2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093 added no prediction STL predictor 2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa added STL predictor module and moved state from SplitLSQ to it 2022-06-08 12:04:25 +01:00
Franz Fuchs
fd639f4b22 added typedef for static number in Ras.bsv 2022-05-14 17:16:40 +01:00
Jonathan Woodruff
9bfaf4cbf0 Swap poliarity of prediction for comparison with upstream. 2022-03-25 14:03:06 +00:00
Jonathan Woodruff
6d7f95571f Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction 2022-03-25 13:06:22 +00:00
Jonathan Woodruff
3cdc2d31c8 Experimentally increase delay before reset. 2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8 Reset counter if head becomes valid. 2022-03-16 11:39:57 +00:00
Jonathan Woodruff
7b78c0ed7b Delay returns (up to 10 cycles) if there is an outstanding push. 2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1 Clean up prints 2022-03-11 10:24:39 +00:00
Jonathan Woodruff
37a7745f1a Fix a few errors in the previous commit, and importantly, make the 
"push" from writeback just a write to the location that was meant to
push to, rather than the current head.
 2022-03-10 11:04:54 +00:00
Peter Rugg
a6976c0071 Fix RVFI-only build 2022-03-09 22:18:08 +00:00
Jonathan Woodruff
9d68d877d9 Move to much simpler design. 
Just update the head in Decode, and write data from Execute.
A loop calling from the same place will at least find the correct
address.
Also, the bad fixup interaction is solved.
 2022-03-09 12:32:01 +00:00
Jonathan Woodruff
bbdcf6dde9 A more sophisticated RAS protection delay. 
Saturate down, and also predict with old push value if there is more
than 6 cycles of delay.
 2022-03-08 15:17:54 +00:00
Jonathan Woodruff
064cd22114 Inteligently delay Decode (for up to 8 cycles) if we encounter a pop 
while waiting for a push.
 2022-03-07 17:52:11 +00:00
Jonathan Woodruff
75d1afe8b4 Only push to RAS when the linking instruction is non-speculative. 
That is, don't push in Decode, push from the training structure coming
from Execute, which is delayed until the instruction that issued it is
non-speculative.
 2022-02-18 13:22:02 +00:00
Jonathan Woodruff
4961d321b9 Merge branch 'CHERI' into jdw57_prediction 2022-02-16 10:10:00 +00:00
Jonathan Woodruff
05df76073b Revert some unintended changes from the last commit. 2022-02-01 11:08:37 +00:00
Jonathan Woodruff
01132d165a Enable tracing of physical addresses for RVFI (if PADDR_RVFI is 
defined).
This is done by adding a vector of padder lookup interfaces to the load
store queue.
This should help with targeted memory translation debugging, and also
with compatability with the current Sail RVFI implemenation which is
probably incorrect with respect to the RVFI spec which calls for virtual
addresses in the maddr field.
 2022-02-01 09:10:48 +00:00
Jonathan Woodruff
ad5d5aca0d Also pause branch execution when there is a pending wrong speculation. 2022-01-31 12:36:17 +00:00
Jonathan Woodruff
a56deab46c Simpelest strategy for making wrongSpec not conflict with loads of 
rules.
This triggers some assertions in the ROB what should be dealt with
properly if this is going to work.
 2022-01-31 12:36:17 +00:00
Jonathan Woodruff
4fbb7b5648 A version that seems to actually run. 
The buffer in GlobalSpecUpdate has to be a SpecFifo.
 2022-01-31 12:09:38 +00:00
Jonathan Woodruff
c1c4a46b1e Simpelest strategy for making wrongSpec not conflict with loads of 
rules.
This triggers some assertions in the ROB what should be dealt with
properly if this is going to work.
 2022-01-31 12:09:38 +00:00
Jonathan Woodruff
4cfd652b0d Use mkRegOR in register file. 2022-01-25 20:42:16 +00:00
Jonathan Woodruff
e497091e18 A timing optimisation for the direction predictor. 
Add a "nextPc" interface so that lookup can begin in the previous cycle.
Remove the "pc" operands in the vector of lookup interfaces,
but rather derive the PC from lookup from the first PC being looked up
in that cycle. That is, by adding 4*(interface number) to the beginning
lookup PC.  As this might not actually be the PC of the instruction,
pass the index you used with the training info so that you are certain
to train with the same index you looked up.

This has less than 1% overhead in CoreMark.

This is a general improvement for reasonable timing which should be upstreamed.
 2022-01-18 11:05:09 +00:00
Jonathan Woodruff
1f8181d595 Move to (recently merged) non-pipelined Divide. 2022-01-13 11:14:20 +00:00
Jonathan Woodruff
37f6dbde93 Timing optimisation for Tournament Predictor. 
Start global-history-indexed lookups in the previous cycle.
This is a general timing optimisation that should be pushed upstream at
some point.
 2022-01-12 16:08:33 +00:00
Jonathan Woodruff
e600fd7d38 Delay BTB update by a cycle for timing. 
This should not be a primary degredation of performance since the
redirection gets on seperately from this update which will only affect
future predictions.
 2022-01-08 10:16:50 +00:00
Jonathan Woodruff
b84562a027 Improve scheduling for LatencyTimer to improve timing path discovered on 
DE10.
 2022-01-07 09:52:43 +00:00
Jonathan Woodruff
f619f4b0a1 Make the associative BTB compressed. 
That is, only store the bottom 16 bits of the target if the upper bits
of pc and nextPc match.
Have a single "way" dedicated to full targets.
 2021-12-20 17:24:55 +00:00
Jonathan Woodruff
54d1a204f0 Don't decode redirected streams until they are non-speculative. 2021-12-17 16:29:14 +00:00
Jonathan Woodruff
4cc86b1e56 Revert more changes to buffer speculative training, as previous 
buffering of training from execute should be sufficient for the BTB as
well.
 2021-12-16 15:01:46 +00:00
Jonathan Woodruff
3322d1d3d7 Revert "An attempt at wiring up the specUpdate interface for the Btb." 
This reverts commit 022df36199.
 2021-12-16 12:10:50 +00:00
Jonathan Woodruff
022df36199 An attempt at wiring up the specUpdate interface for the Btb. 2021-12-15 18:40:58 +00:00
Jonathan Woodruff
696f546ecb Version using searchableSpecFifo in BTB with actual searching, but 
without killing speculative elements yet. This one is full performance
in CoreMark.
 2021-12-15 18:27:45 +00:00
Jonathan Woodruff
657453a0a0 Two modules (that build) that should be helpful in delaying the commit 
of training data.
 2021-12-15 17:06:46 +00:00
Jonathan Woodruff
af69f2e5db Merge branch 'CHERI' into jdw57_prediction 2021-12-15 16:47:42 +00:00
Jonathan Woodruff
34c6ee1894 Specifically give priority to wrong_spec when they conflict. 
This appears to yield 10% performance improvement as our default setup
appears to choose a wrong priority.
 2021-12-03 12:36:40 +00:00