Cheri-research/Toooba
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ad044689cb11675239b6c8670bc47fb27557db1c
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212 Commits

Author SHA1 Message Date
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00
Jonathan Woodruff
2bfe25dfad Update Map.bsv 
Remove unused function.
 2021-03-22 20:28:34 +00:00
jon
d351eeee11 Increase BTB to 1024 entries. 
(On FPGA we can make this as large as we like, but returns diminish.
This one has a chance of being reasonable for ASIC I guess?)
 2021-03-22 18:20:22 +00:00
jon
30bd5e7f46 Allow entries in the load kill predictor to be "False" so that they can 
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.

Remove debugging prints.
 2021-03-22 18:14:33 +00:00
jon
791927f852 Prediction for whether a load will have an aliasing store. 2021-03-22 18:14:33 +00:00
jon
8de3cfffeb Remove debug print statements. 2021-03-10 17:03:35 +00:00
jon
fe7977e4e9 Fix typo when removing commented out code. 2021-03-06 07:24:49 +00:00
jon
8da520175f Use an (unguarded) BRAM in the Btb. 
Also, assume that a target that is not taken should be removed from the
Btb.  (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
 2021-03-06 07:19:50 +00:00
jon
4b411bf752 A Btb with 1/4 the storage that will (hopefully) infer as BRAM. 2021-03-05 12:14:26 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
jon
c515fb4518 Remove commented-out code. 
Enable building with open-source BSC.

Resolve a couple issues brought up by Jess.

Remove a stray space (as noted by Jess).
 2021-01-14 17:10:04 +00:00
jon
fc968c867f PC compression scheme for the instruction fetch pipeline. 
Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.
 2021-01-14 11:41:11 +00:00
jon
0d93ed3ad2 Merge branch 'CHERI' into ifetch-cleanup 2021-01-13 15:21:20 +00:00
Jonathan Woodruff
92ca72a6e2 Fix build error by providing default. 2020-12-18 17:55:18 +00:00
Jonathan Woodruff
84d60d03b1 Merge pull request #6 from nwf/capdirty 
CHERI ISAv8 CapDirty fault priority fix
 2020-12-18 16:48:56 +00:00
jon
f86d4d9dc0 Add counter support to ITLB. 2020-12-17 17:57:43 +00:00
jon
4ddcaff497 Support for data TLB counters. 2020-12-17 16:52:45 +00:00
jon
bab989d6d2 Support for stat counters from the tag controller. 
The order of the events is very not tested; 50% chance of being correct.
 2020-12-17 12:38:52 +00:00
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
Jessica Clarke
f6569e2d14 Actually do the intended fix, not just inverting the variable 2020-12-14 10:51:57 +00:00
Jessica Clarke
295b878836 Fix negated CYCLE/INSTRET logic for ASR and make less confusing 2020-12-14 10:50:23 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
f42c3f3577 Merge branch 'cheri-perfmon' into CHERI 2020-12-04 16:29:51 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Nathaniel Filardo
6e4c378d4d CHERI ISAv8 CapDirty fault priority fix 
Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
 2020-11-06 19:15:47 +00:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00
jon
1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. 
(Previously we ran into the limit of ports on the regFiles holding state
in the BTB.  This uses a vector of regFiles with a vector of interfaces,
which is logically the same but might produce multiple copies of state.)
 2020-09-16 11:42:19 +01:00
jon
96afb0a7f5 FIFO optimisation both for build time (and possibly condition 
complexity?) and for throughput.
 2020-08-13 17:33:46 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00