This includes renaming Fifo.bsv to Fifos.bsv to account for a case insensitive file system which confuses this library with FIFO.bsv.
Also this includes an update of the verilator flags that are needed for modern verilator.
Finally, some verilator flag changes for building with LLVM.
Two of these were not properly restricted as read-only from CSRRX instructions,
and there was a bug in the WARL function for writing MIP,
and there was a bug in the TV-reporting of MIP updates.
When a CSRRx instruction writes to FCSR/FFLAGS/FRM, the CPU also
changes MSTATUS.FS and, by implication, MSTATUS.SD because the
floating point state has become "dirty". Tandem Verification
trace-generation was not reporting this update.
PLIC: updated to latest version from Piccolo/Flute.
MMIO_AXI4_Adapter: added workaround for Xilinx IP problem on 64-bit
AXI4 fabrics. Writes that specify 8-byte size, but only write in
upper or lower word using strobes, are converted into 4-byte size.
Core.bsv: added a notification to the Debug Module re. CPU halt.
MIP/MIE/SIP/SIE fields are WARL (Write-Any/Read-Legal). The CSR
register forces the user-privilege bits ([8,4,0]) to 0 since riscy-ooo
does not support user-level interrupts. However, function
Csrfile.fv_warl_xform() was not mirroring this correctly.
(1) riscy-ooo was mapping all unimplemented CSRs to a benign, user-privilege read-write CSR
Instead, we now catch this RenameStage and steer it to a trap.
(2) MSTATUS.FS was initialized to 2'b00 (absent/off); should be 2'b01 (present and initial)
Previously, the request went out into the fabric, and we were relying
on the fabric returning an error response. Some fabrics don't do this
reliably, so this removes that reliance on the fabric.
src_Core/CPU/CsrFile.bsv
Various fixes for WARL'd values of mstatus and sstatus, medeleg,
Added tval field in Trap_Updates returned by csrf.trap
src_Core/Core/Trace_Data2.bsv
Added fields for store_data and store_data_BE
src_Core/Core/Trace_Data2_to_Trace_Data.bsv
Added treatment of store_data and store_data_BE
Fixed bug in next_pc for mkTrace_RET
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Fixed Trace_Data2 struct to TV for pc in case of xRET, and tval in case of trap
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
Added store_data and store_data_BE in calls to rob_setExecuted_doFinishMem
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Added store_data and store_data_BE in methods rob_setExecuted_doFinishMem
Now able to run multiple ISA tests in a single simulation run
connected to remote debugger DSharp, using either hart_reset or
ndm_reset between tests to bring the system back into reset state.
All Debug Module commands working:
- dm_reset, hart_reset, ndm_reset
- break (set breakpoint)
- step
- continue (until breakpoint of 'halt' command)
- halt
- read/write GPR, FPR, CSR, memory
- elf_load
After a test, GDB can write DCSR to restore to Machine privilege,
write to PC (DPC) to restore boot value,
write MSTATUS to restore to initial value,
then can load and run next test.
When controlled from a debugger (build with INCLUDE_GDB_CONTROL macro);
when stopped due a EBREAK instruction; on a 'resume' command ('continue' in GDB),
was getting stuck. This is now working.
At this point, all debugger functionality (almost: see below) is working:
halt, step, breakpoints, resume, read/write gpr/fpr/csr, read/write memory.
Still todo: "NDM reset" (non-debug module reset).
Detail: an "instruction-fetch" response from mmioplatform to core
should be an "InstFetch". This was true for successful fabric reads,
but on error responses it was wrongly returned as a "DataAccess"
response. This was causing a deadlock.
Modified:
src_Core/RISCY_OOO/procs/lib/L2Tlb.bsv
In rule doPageWalk, if (!leafPte) ... else: added check for PPN alignment.
(In mega-/giga-page PTEs, lower bits of PPN must be zero for alignment)
Modified:
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
Bug fixes in 'getTrap' function:
- Trap if Fpu regs are accessed but mstatus_fs is "Off" (2'b00)
- Trap if r/w or privilege denies access to CSR in CSRRW/C/S instruction
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
Bug fix: add support for 'u' bit in function 'getExtensionBits'
Regression status: RV64ADFIMSU_Toooba_verilator 204/229 PASS
(22 expected floating-point failures due to inaccurate modeling)
Modified
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
Renamed 'BootRom' to 'IODevice'
Imported and instantiated SoC_Map
changed method getFetchTarget to use soc_map.is_IO_addr (phyPC)
to classify as IODevice
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Changed 'BootRom' constant to 'IODevice' constant (just a renaming)
src_Testbench/SoC/SoC_Map.bsv
Changed boot rom classification from 'mem' to 'IO device'
Modified
src_Core/CPU/MMIO_AXI4_Adapter.bsv
Instead of aborting on axi4 mem read error, pass the error on to the core
src_Core/RISCY_OOO/procs/lib/MMIOAddrs.bsv
Added mainMemBoundAddr
src_Core/RISCY_OOO/procs/lib/MMIOCore.bsv
Update isMMIOAddr check to also check mainMemBoundAddr
src_Core/RISCY_OOO/procs/lib/MMIOInst.bsv
Update getFetchTarget to also check mainMemBoundAddr
(still TODO: allow other IO addrs other than bootRom)
Modified:
src_Core/CPU/CsrFile.bsv
Modified method 'trap' to use 'addr' for trap_val (MTVAL) instead of PC
for InstAccessFault and InstPageFault
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Added 'tval' field to Fetch2Fetch3; set the value on TLB faults; send it out in 'FromFetchStage' struct
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
In rule doRenamingTrap, pass tval from FromFetchStage struct to ToReorderBuffer struct
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Add 'tval' Ehr to reorderbuffer slot, to accompany 'trap' Ehr.
In method write_enq, store tval from ToReorderBuffer arg into tval Ehr.
In method read_deq, send 'tval' Ehr value into 'ToReorderBuffer' output (goes to CommitStage)
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Modified rule doCommitTrap_flush to take tval from 'ToReorderBuffer' input from ROB,
for InstAccessFault and InstPageFault
LICENSE
README.md
Clarified licensing of MIT code and Bluespec code
Tests/Run_regression.py
Emptied out 'exclude_list'
builds/RV64ADFIMSU_Toooba_verilator/Makefile
Added 'C' to Makefile
>----------------
Status and outlook:
For RV64GC, out of 229 standard ISA tests, 202 PASS, 27 FAIL.
Below is a list of current failures, current diagnoses, and outlook.
'C' instructions:
rv64uc-v-rvc
Diagnosis: error in saved regs during instruction page fault
when a 32-bit instruction straddles a page boundary and
the second 16-bits encounters a page fault.
Note: the corresponding rv64uc-p-rvc passes, containing
the same set of tests except for the virtual-memory
aspect, so we expect this test to pass once this issue is
fixed.
Outlook: Target date for fix: 2019-Apr-09 (today)
System instructions:
rv64mi-p-access
rv64mi-p-csr
rv64si-p-dirty
rv64mi-p-illegal
Diagnosis: we do not have accurate diagnoses yet, although
some symptoms look similar to what we saw with earlier
processors (these test various corner-cases of system
instructions).
Outlook: Target date for fix: 2019-Apr-15
'F' and 'D' instructions
rv64uf-p-fadd rv64uf-v-fadd
rv64uf-p-fcmp rv64uf-v-fcmp
rv64uf-p-fdiv rv64uf-v-fdiv
rv64uf-p-fmin rv64uf-v-fmin
rv64ud-p-fadd rv64ud-v-fadd
rv64ud-p-fcmp rv64ud-v-fcmp
rv64ud-p-fdiv rv64ud-v-fdiv
rv64ud-p-fmadd rv64ud-v-fmadd
rv64ud-p-fmin rv64ud-v-fmin
rv64ud-p-ldst rv64ud-v-ldst
rv64ud-p-move rv64ud-v-move
Diagnosis: These seem to be simulation-only errors. Simulation
uses some quick-and-dirty floating-point "model" modules
written by the MIT authors, which are not accurate. All
the errors seem to be regarding incomplete treatment of
NaNs in the models. These errors should not happen in
FPGA since those use Xilinx IP modules instead. MIT has
been booting Linux with the Xilinx IP modules, lending
more confidence in the FPGA version.
The actual number of root-cause failures is likely to be
smaller than the list. For example, the 'fadd' test has
four variants: {uf/ud} x {-p-/-v-}; they all likely need a
comon fix.
Outlook: Target date: 2019-Apr-30
[Lower priority, since FPGA versions should be ok even now.]
>----------------
Detailed comments on file changes
New files:
Doc/micro2018.pdf
MIT's paper on RISCY-OOO at IEEE Micro
src_Core/CPU/CPU_Decode_C.bsv
Function to expand 'C' instrs to 32-bit counterparts, taken from Piccolo/Flute
Modified files:
src_Core/CPU/Core.bsv
Added rob_getOrig_Inst method
src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
Added 'orig_inst' stuff, $displays
src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv
Mostly verbosity stuff, including printing out brief instruction trace similar to Piccolo/Flute.
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
Major changes for 'C', including call to Decode_C function from Piccolo/Flute
Pass orig_inst to downpipe.
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
Added 'orig_inst', input from FetchStage and passed on to ROB
Tweaked PC+4 check to accommodate 'C' instructions.
src_Core/RISCY_OOO/procs/lib/BrPred.bsv
Fixed 'decodeBrPred' to accommodate 'C' instructions
src_Core/RISCY_OOO/procs/lib/Exec.bsv
Fixed 'brAddrCalc', 'getControlFlow', 'basicExec' to acommodate 'C' instructions
src_Core/RISCY_OOO/procs/lib/MemLoader.bsv
Switched off 'verbose' by default
src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv
Added 'C' to MISA, 'getExtensionBits'
src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv
Added 'orig_inst' register to basic cell, and methods to set/access.
src_Core/RISCY_OOO/procs/lib/Types.bsv
Added typedefs for 'C' instructions
>----------------
