Cheri-research/Toooba
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Author SHA1 Message Date
jon
9508eada79 Change to allow 1-way superscalar to build without error. 2020-09-17 14:40:46 +01:00
jon
1568fcf485 Enable larger than 2x superscalar by using explicit ports into the BTB. 
(Previously we ran into the limit of ports on the regFiles holding state
in the BTB.  This uses a vector of regFiles with a vector of interfaces,
which is logically the same but might produce multiple copies of state.)
 2020-09-16 11:42:19 +01:00
jon
96afb0a7f5 FIFO optimisation both for build time (and possibly condition 
complexity?) and for throughput.
 2020-08-13 17:33:46 +01:00
jon
4c74d27e4e Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:31:30 +01:00
jon
7a93056b8b Increase the capacity of f32d to enable full throughput. 
I don't know why this is necessary, but this allows performance parity
with the baseline.
 2020-08-11 15:30:03 +01:00
jon
9230fcc3b4 Merge branch 'CHERI' into ifetch-cleanup 2020-08-11 15:25:12 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
jon
3b97fbe255 Rename last->prev for clarity. 2020-07-31 13:46:33 +01:00
jon
f63673c3f3 First working implementation of the new instruction picker. 
Evidence of "working" is passing TestRIG to a cursory depth including
compressed instructions and running CoreMark in simulation.
This one appears to be 2.5% slower than the existing design in CoreMark,
so some optimisation should be done.  We expect it to be a bit faster
than the original due to more flexibility in decoding instructions from
different fetch units together.
 2020-07-31 11:25:28 +01:00
jon
3a9e76c1fd Fix bug where the wrong bounds were attached to a mispredicted half of 
an instruction.
 2020-07-29 12:32:28 +01:00
jon
8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." 
This reverts commit 4fe24c9cd5.
 2020-07-29 11:40:00 +01:00
jon
4fe24c9cd5 Remove the special flush from the Fetch3 stage. 
This is an intermediate simplification for moving to SupFifo-based picking.
 2020-07-29 07:40:15 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00
Jessica Clarke
73dedec309 FetchStage: Use map rather than for loop 
Also add some spaces in the following line.
 2020-07-24 20:02:10 +01:00
Jessica Clarke
0b3ad23c24 Fix typo 2020-07-24 19:10:11 +01:00
Jessica Clarke
1bad5b080b Various updates to README.md 
* Fix the arch string
 * Document the RVFI-DII build directories
 * Don't tell people to build RTL using them
 * Bluesim build configurations exist
 2020-07-24 19:06:56 +01:00
Jessica Clarke
44d49a52c0 Drop removed CHERI directory from README.md (Closes: #3) 
27947f4df7 moved the SCRs into the main
CSR register file, and that was the only thing in this directory.
 2020-07-24 18:47:26 +01:00
jon
40af067a71 Fix RVFI_DII build in the presence of 2-byte bundles. 2020-07-24 17:30:29 +01:00
jon
1f968b0c07 2-byte aligned instruction memory to simplify compressed instruction 
fetch.
 2020-07-24 12:38:37 +01:00
Peter Rugg
ecce475b97 Merge branch 'mem_perm_checks' into CHERI 2020-07-23 16:53:14 +01:00
Peter Rugg
27082ee2a9 Report writes to PCC as illegal instruction, not ASR violation 2020-07-23 15:40:28 +01:00
Peter Rugg
97d89086a6 Bump cheri-cap-lib 2020-07-23 11:20:30 +01:00
Peter Rugg
e8aa873c2e Prevent 'insufficient type info' warning 2020-07-23 11:18:31 +01:00
Peter Rugg
a6b40e946b Prevent using CCSeal to 'seal over' other types 2020-07-23 11:18:07 +01:00
Peter Rugg
c693462f6b Add tag-clearing due to cap load perm and PTE bits 2020-07-22 15:54:49 +01:00
Peter Rugg
0040b05ada Add page table cap store checking 2020-07-21 16:02:37 +01:00
Jessica Clarke
2f4f5ca838 FetchStage: Reduce diff to upstream 2020-07-21 14:36:36 +01:00
Jessica Clarke
0516db5e8d Bump BSV-RVFI-DII and refactor to support new parcel-based interface 
This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
 2020-07-21 14:36:36 +01:00
jon
7d98946103 Working compressed instruction support. 2020-07-20 19:49:52 +01:00
jon
d7a4d3497b Keep unaligned instruction fetch from breaking DII. 2020-07-17 16:39:13 +01:00
jon
4d2f971767 Assign the correct PC to fetched instructions. 2020-07-17 11:07:19 +01:00
Jessica Clarke
72f49a1109 Regenerate verilog 2020-07-16 19:35:51 +01:00
Jessica Clarke
2b8e5f1dad FetchStage: Inline unnecessary local variable 2020-07-16 18:13:43 +01:00
Peter Rugg
a74596c956 Fix CCall being impossible 
The cap to be checked (rs1) was being overwritten with the unsealed jump
target before the type was checked
 2020-07-16 14:06:26 +01:00
Jessica Clarke
5efd7d5cd8 Partially bring back tval 
We need this to determine which 16b parcel of a 32b instruction caused
the fault (omitting this caused rv64uc-v-rvc to fail).
 2020-07-15 04:27:25 +01:00
Jessica Clarke
682ff10d72 Regenerate verilog 2020-07-15 03:16:24 +01:00
Jessica Clarke
7eff218288 Replace enums-for-constants with structs wrapping a plain Bit#(n) 
BSC does not play nicely with enums whose labels do not start at 0 and
increase linearly. Instead, in such cases, it generates a whole bunch of
conditions to "legalise" any read values, which causes an explosion of
logic in places like the ROB. Thus, use this ugly (but still typed)
alternative that, other than naming conventions enforced by BSC, looks
almost the same as an enum.
 2020-07-15 03:16:24 +01:00
Jessica Clarke
b65576b112 Copy TAP file generation code from Flute 2020-07-15 03:16:24 +01:00
Peter Rugg
b44a912756 Don't require ASR to read PCC 
The dInst.scr field was accidentally left populated in this case,
causing the check to occur
 2020-07-14 22:41:51 +01:00
Jessica Clarke
e8c1de7793 Regenerate verilog 2020-07-14 19:01:47 +01:00
Jessica Clarke
956c9686a6 src_SSITH_P3: Optimise unspecified values 
We have a lot of ?s floating around that needlessly constrain logic. As
with Flute, enable optimisations on these in the hope that timing and/or
area improve further.
 2020-07-14 17:53:01 +01:00
Jessica Clarke
6356d5f8a1 Drop check against whether the ROB row already has a trap 
The only other thing setting this is enq, but RenameStage marks
already-trapping instuctions as Executed so they should never go to the
ALU.
 2020-07-14 16:46:29 +01:00
Jessica Clarke
f2d9c78824 Drop unused exception parameter on FPU ROB ports 
This gives traceBundle its own set of ports. Also fix the nonsensical
calculations for those Ehr ports; the number of FPUs should not be
calculated as ALUs/2!
 2020-07-14 16:37:59 +01:00
Jessica Clarke
0b7d635cbf Drop unused store_data/store_data_BE arguments when TV is disabled 2020-07-14 16:23:10 +01:00
Jessica Clarke
5a42b0102a Turn pc back into a Reg 
This is from before we fed bounds all the way back to the BTB and RAS.
We no longer need this and can go back to what upstream does.
 2020-07-14 16:22:52 +01:00
Jessica Clarke
9bdf71ee4e Only store the actual address for completed loads/stores 
This is only needed for RVFI tracing and for xtval if we trap, so we
never need the full capability.
 2020-07-14 16:22:50 +01:00
Peter Rugg
675caad0ac Trap for permission failures on mem access 2020-07-14 15:34:38 +01:00
Jessica Clarke
e89f7a8130 Regenerate verilog 2020-07-13 18:54:53 +01:00
Jessica Clarke
26a5376f9c FetchStage: Tidy up comment that no longer applies 
Block is now entirely for debugging only.
 2020-07-13 18:23:01 +01:00
jon
83b734ed87 Remove commented-out code. 2020-07-13 18:20:56 +01:00