This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
See 2d7ae22c0a for corresponding Sail change
This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
Also, 16-bit hashed tags. (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.
Remove debugging prints.
Also, assume that a target that is not taken should be removed from the
Btb. (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.
Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.
This fixes the rv64si-p-dirty ISA test, currently the sole failure.
Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.
Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
