Cheri-research/Toooba
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Commit Graph

234 Commits

Author SHA1 Message Date
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
4ae9f5346c Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-06-01 15:18:29 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Peter Rugg
88751cccba Remove hardcoded field encodings for cap loads and stores 2021-05-26 16:25:55 +01:00
Peter Rugg
913d14406e Add explicit PCC and cap JALRs 2021-05-26 16:24:41 +01:00
Peter Rugg
6450d9c33c Make JAL and JALR mode-dependent 2021-05-26 16:24:41 +01:00
Peter Rugg
657124671c Support amoswap.c 2021-05-13 23:15:25 +01:00
Peter Rugg
abc70134b1 Don't take load cap page faults if the authorising cap doesn't have load cap 2021-05-13 23:15:25 +01:00
Peter Rugg
7e77b2314b Clarify precedence in VM permission check 2021-05-05 13:32:07 +01:00
Peter Rugg
e7258f0f22 Plumb through info on whether a load is capWidth to the TLB 2021-05-05 13:32:07 +01:00
Peter Rugg
48e22af43e Factor out PTE cap invalid check 2021-04-29 16:02:30 +01:00
Peter Rugg
005ba1bd6f Add LoadCapPageFault exception cases 2021-04-29 16:02:30 +01:00
Peter Rugg
3b07a2a17c Add revocation 3.0 bits 2021-04-29 16:02:30 +01:00
jon
7cefaacb86 Remove wayward disabling of consistency flush case for the weak memory 
model.
 2021-04-21 10:44:31 +01:00
jon
2c41fcd7fb Fix bug and improve expression by using Int. 2021-04-12 12:48:49 +01:00
jon
4776bc0a11 Double-train on killing a load (still decrement by one on success). 
This combo got the best performance overall (I tested triple and
quadruple training).
 2021-04-12 06:34:16 +01:00
jon
8e3fd534f9 Do negative training when we encounter a load that has previously been 
killed, but was not killed this time.
 2021-04-10 08:47:05 +01:00
jon
aa9e57ce10 Fix bug so that we actually start at minBound. 
(Map defaults to unpack(0), so for an Int, our first updateFunc will add
one to zero and it won't be much different than before.)
 2021-04-10 07:54:39 +01:00
jon
6b871c0442 Use a saturating add before being conservative with issuing loads. 2021-04-09 16:21:55 +01:00
Peter Rugg
fcea5365f6 Initial implementation CLoadTags 
This currently just loads in the data on cache miss, so won't help to reduce DRAM overhead, but will be forwards compatible and save on instructions in the revoker loop.
 2021-04-08 17:08:15 +01:00
Peter Rugg
b232272ad1 Treat CCSeal with an out-of-bounds capability as a move 
See 2d7ae22c0a for corresponding Sail change

This is not the nicest approach for area, but integrating with the existing bounds check would delay the result a cycle, and incur additional complexity.
 2021-04-08 13:08:46 +01:00
jon
12ac14c1ca Move to config registers here as this affects scheduling. 2021-04-07 17:47:49 +01:00
Franz Fuchs
ad044689cb added some of the performance counters in the L2 TLB 
- count L2 TLB accesses
- count L2 TLB misses
- count L2 TLB flushes
 2021-04-01 16:18:18 +01:00
jon
c17eb9e7c1 Finish propagating BTB name change from previous commit. 2021-04-01 09:04:31 +01:00
jon
0701dea9a9 Preserve name for verilog so component.xml doesn't have to be fixed. 2021-04-01 07:08:46 +01:00
Franz Fuchs
4b531fac46 Made the hash size in the BTB configurable 
The current configuration is a tag of 16 bits width
 2021-03-31 17:46:27 +01:00
jon
5e687a972a Slight cleanups from review with Alexandre. 2021-03-24 12:21:00 +00:00
jon
07dd70d77b Associative 2-way associative BTB. 
Also, 16-bit hashed tags.  (This is because the only full-speed
implementation required duplicating the tags).
This implementation uses the MAP library, and a new BRAM instance of it.
 2021-03-24 09:56:25 +00:00
jon
20e2249761 Make map associative in preparation for associative BTB. 
Also make jump alias predictor smaller and associative.  (2x64 entries
instead of 256 entries)
 2021-03-23 11:26:43 +00:00
Jonathan Woodruff
2bfe25dfad Update Map.bsv 
Remove unused function.
 2021-03-22 20:28:34 +00:00
jon
d351eeee11 Increase BTB to 1024 entries. 
(On FPGA we can make this as large as we like, but returns diminish.
This one has a chance of being reasonable for ASIC I guess?)
 2021-03-22 18:20:22 +00:00
jon
30bd5e7f46 Allow entries in the load kill predictor to be "False" so that they can 
be invalidated.
Also invalidate entries "randomly" to prevent a steady-state of waiting
for all stores to complete on 1/256 loads even when no aliasing is going
on.

Remove debugging prints.
 2021-03-22 18:14:33 +00:00
jon
791927f852 Prediction for whether a load will have an aliasing store. 2021-03-22 18:14:33 +00:00
jon
8de3cfffeb Remove debug print statements. 2021-03-10 17:03:35 +00:00
jon
fe7977e4e9 Fix typo when removing commented out code. 2021-03-06 07:24:49 +00:00
jon
8da520175f Use an (unguarded) BRAM in the Btb. 
Also, assume that a target that is not taken should be removed from the
Btb.  (The read that checked isn't possible with BRAM timing unless we
latched and had an extra port, but removing the check actually improved
performance a bit in CoreMark, and the pipeline should actually only be
reporting a non-taken branch if we did something wrong.)
 2021-03-06 07:19:50 +00:00
jon
4b411bf752 A Btb with 1/4 the storage that will (hopefully) infer as BRAM. 2021-03-05 12:14:26 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
jon
c515fb4518 Remove commented-out code. 
Enable building with open-source BSC.

Resolve a couple issues brought up by Jess.

Remove a stray space (as noted by Jess).
 2021-01-14 17:10:04 +00:00
jon
fc968c867f PC compression scheme for the instruction fetch pipeline. 
Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.
 2021-01-14 11:41:11 +00:00
jon
0d93ed3ad2 Merge branch 'CHERI' into ifetch-cleanup 2021-01-13 15:21:20 +00:00
Jonathan Woodruff
92ca72a6e2 Fix build error by providing default. 2020-12-18 17:55:18 +00:00
Jonathan Woodruff
84d60d03b1 Merge pull request #6 from nwf/capdirty 
CHERI ISAv8 CapDirty fault priority fix
 2020-12-18 16:48:56 +00:00