Karlis Susters
bd2ceec15f
L1D prefetch into S, not M
2023-02-20 11:17:59 +00:00
Karlis Susters
2c9428d1f3
Prepared repo for building on FPGA
2023-02-13 21:52:50 +00:00
Karlis Susters
9d027a3f4b
Implemented BRAM versions of stride, target, markov prefetchers
2023-02-13 11:59:26 +00:00
Karlis Susters
31ae938e78
Implemented a stride prefetcher with BRAM instead of vectors
2023-02-13 11:59:26 +00:00
Karlis Susters
79c55c5651
Implemented cross cache prefetching, fixed some coherence bugs in LLC
2023-02-13 11:59:26 +00:00
Karlis Susters
dca4b980c5
Implemented a markov chain data prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
9f733eddf1
Merged reportHit & reportMiss, changed compile time parameter passing
2023-02-13 11:59:26 +00:00
Karlis Susters
06e648df6a
Implemented target table module, refactored single and multi window instruction prefetchers to use it
2023-02-13 11:59:26 +00:00
Karlis Susters
7c05ebbd90
Implemented multi line target prefetcher
2023-02-13 11:59:26 +00:00
Karlis Susters
e602d4780e
LLC prefetcher fixes and single window target prefetcher implementation
2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733
Prefetcher implementation in both L1 and LL and data logging
2023-02-13 11:59:26 +00:00
Peter Rugg
6931201a14
Avoid wedge on repeated debug resumes (with jdw57 and aj443)
...
ConfigReg avoids a compile error
2023-01-31 21:02:17 +00:00
Peter Rugg
e120b3427d
Merge branch 'LoadTagsImprove' into CHERI
2022-11-14 13:28:44 +00:00
Franz Fuchs
de0e19ca55
added do not cares for missing struct fields in ROB
2022-10-21 09:22:31 +00:00
Alexandre Joannou
d068df3bd8
uncomment a verbosity check
2022-09-02 12:37:07 +00:00
Jonathan Woodruff
1fceb8fa72
Use standard imports as the fixes have been upstreamed.
2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b
NonPipelined API update
2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a
Bump BlueStuff + add outter subordinate trafic as master to internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38
Use NonPipelined dividers + update "reset_by" in CoreW
2022-08-15 16:18:23 +00:00
gameboo
45135a0bee
Don't assume a XILINX tool flow
2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c
Fixes for load address tracing.
2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4
commented out debug print statements in Ras.bsv
2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d
added typedefs to STLPred
2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90
removed unnecessary declarations in RenameStage
2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0
Fix tracing of writes to MMIO addresses.
2022-07-22 15:37:25 +00:00
Franz Fuchs
502e64c24b
fixed not defined warning in ConnectalBramFifo
2022-07-11 15:11:59 +01:00
Franz Fuchs
4abf838d62
implemented missing notFull method in SpecFifo
2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d
used RVFI defines as declared in ToReorderBuffer
2022-07-11 14:18:19 +01:00
Alexandre Joannou
9960d67ed8
Removed some debug print statements
2022-07-11 11:55:40 +00:00
Franz Fuchs
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc
Attempt to clear tag on exception path before forwarding.
...
This is likely to be bad for timing, but might just work at 25MHz.
2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a
corrected ifdef in STLPred.bsv
2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093
added no prediction STL predictor
2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa
added STL predictor module and moved state from SplitLSQ to it
2022-06-08 12:04:25 +01:00
Peter Rugg
b113d05095
Prioritise misaligned over RVFIDII load access fault
2022-05-18 14:59:43 +01:00
Franz Fuchs
fd639f4b22
added typedef for static number in Ras.bsv
2022-05-14 17:16:40 +01:00
Peter Rugg
8ba929438d
Fix cloadtags in LLC
2022-03-31 02:07:01 +01:00
Peter Rugg
6d4644ce73
Add tag-only state to MESI and interface with tagOnlyReq of tag controller
2022-03-31 02:07:01 +01:00
Jonathan Woodruff
9bfaf4cbf0
Swap poliarity of prediction for comparison with upstream.
2022-03-25 14:03:06 +00:00
Jonathan Woodruff
6d7f95571f
Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction
2022-03-25 13:06:22 +00:00
Jonathan Woodruff
3cdc2d31c8
Experimentally increase delay before reset.
2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8
Reset counter if head becomes valid.
2022-03-16 11:39:57 +00:00
Jonathan Woodruff
7b78c0ed7b
Delay returns (up to 10 cycles) if there is an outstanding push.
2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1
Clean up prints
2022-03-11 10:24:39 +00:00
Jonathan Woodruff
37a7745f1a
Fix a few errors in the previous commit, and importantly, make the
...
"push" from writeback just a write to the location that was meant to
push to, rather than the current head.
2022-03-10 11:04:54 +00:00
Peter Rugg
a6976c0071
Fix RVFI-only build
2022-03-09 22:18:08 +00:00
Jonathan Woodruff
9d68d877d9
Move to much simpler design.
...
Just update the head in Decode, and write data from Execute.
A loop calling from the same place will at least find the correct
address.
Also, the bad fixup interaction is solved.
2022-03-09 12:32:01 +00:00
Jonathan Woodruff
bbdcf6dde9
A more sophisticated RAS protection delay.
...
Saturate down, and also predict with old push value if there is more
than 6 cycles of delay.
2022-03-08 15:17:54 +00:00
Jonathan Woodruff
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop
...
while waiting for a push.
2022-03-07 17:52:11 +00:00
Jonathan Woodruff
c17874bdba
Add options to disable each of 5 aspects of enforcment of the Branching
...
Speculation Contract.
2022-02-22 16:21:53 +00:00
