Alexandre Joannou
95f554dad1
removed coreW from component.xml
2022-08-16 12:44:00 +00:00
Alexandre Joannou
a4606c6761
Brought the src_SSITH_P3 folder up to date
2022-08-15 16:18:23 +00:00
Alexandre Joannou
bb62b703c8
Address some rebase nonsense
2022-08-15 16:18:23 +00:00
Franz Fuchs
1bea2c6af2
added missing character to Makefile
2022-07-06 08:31:43 +01:00
Franz Fuchs
0dd65a937f
enabled full BSC build
2022-07-05 12:09:26 +01:00
Franz Fuchs
92b096472a
do configuration for base protection version of Toooba
2022-07-01 10:19:26 +01:00
Franz Fuchs
45b3eaf09c
correct SSITH Makefile
2022-06-30 12:57:07 +01:00
Franz Fuchs
c85b13c5af
added MELTDOWN_CF ifdef and enabled it
2022-06-30 12:55:53 +01:00
Franz Fuchs
82adf5e869
attempt to get new performance numbers
2022-06-29 17:42:38 +01:00
Franz Fuchs
40cfd0e97c
removed PUSH_DELAY from gfe-synth build
2022-06-16 08:56:07 +01:00
Franz Fuchs
1ab18ab6ee
full BSC protection for gfe-synth build
2022-06-15 06:07:36 +01:00
Franz Fuchs
b79a228093
added no prediction STL predictor
2022-06-08 12:23:35 +01:00
Jonathan Woodruff
25013c9713
Revert to including performance improvements by default.
2022-03-29 10:26:35 +00:00
Jonathan Woodruff
c273314084
Remove all BSC protections in an attempt to get a baseline bitfile for
...
that work.
2022-03-29 10:17:12 +00:00
Jonathan Woodruff
163ca1d099
Use only parameters that improve performance.
2022-03-25 14:08:43 +00:00
Jonathan Woodruff
ad7bcbb559
Temprarily remove all protections for a baseline bitfile.
2022-03-25 11:09:32 +00:00
Jonathan Woodruff
3248e42485
Temporarily turn off late push so we can run benchmarks for non-push
...
case.
2022-03-21 10:14:08 +00:00
Jonathan Woodruff
064cd22114
Inteligently delay Decode (for up to 8 cycles) if we encounter a pop
...
while waiting for a push.
2022-03-07 17:52:11 +00:00
Jonathan Woodruff
6d65de5c88
Experimentally remove delayed RSB_PUSH for synthesis.
2022-02-24 11:49:35 +00:00
Jonathan Woodruff
6ea972931d
Add missing verilog file that is inadvertantly used.
2022-02-23 16:46:43 +00:00
Jonathan Woodruff
28646b252d
Add BSC protections to the hardware makefile.
2022-02-23 11:43:41 +00:00
Franz Fuchs
df74a71d61
changed _Synth to _Sig following the new convention in BlueStuff
2021-09-30 15:02:47 +01:00
Franz Fuchs
b4fe3ee93c
adjusted SSITH_P3 Makefile to new version of HPM Events
2021-09-30 13:33:26 +01:00
Jonathan Woodruff
c379a7a293
Changes to build with the new stat counters.
2021-09-24 13:18:55 +00:00
Peter Rugg
ac89600601
Add missing TSO dummy store buffer to component.xml
2021-04-23 16:33:26 +01:00
Peter Rugg
10b5cd7ad7
Switch to TSO
2021-04-22 18:22:02 +01:00
Peter Rugg
53549e0dbc
Set number of cores using RISCY config instead of manual define
...
This was leading to -D NUM_CORES=2 -D NUM_CORES=1 in the command.
The NUM_CORES=2 seems to have been winning, but this is obviously
far from ideal.
2021-04-12 13:10:12 +01:00
Marno van der Maas
3f059cbd94
Added note on bsc-contrib dependency to SSITH readme
2021-04-07 11:53:48 +01:00
Marno
47cddd8ec9
Reverted back to using FPGA specific memory addresses
2021-03-19 15:54:53 +00:00
Marno
dbc1443bf2
Also using new tagsparams API in SSITH build
2021-03-19 15:30:11 +00:00
Peter Rugg
057964e940
Some more tagsparam makefile fixes
2021-03-18 11:09:26 +00:00
Peter Rugg
80fb97cc62
Take Bluestuff-ified Giraffe_IFC from Flute
2021-03-15 12:25:38 +00:00
Peter Rugg
395a9d1c02
Remove unused non-existent libraries from ssith Makefile
2021-03-15 11:26:24 +00:00
Peter Rugg
0e1e2249a6
Default to dual-core builds
2021-03-04 11:54:35 +00:00
Jonathan Woodruff
db08e96596
Add Btb to the component.xml.
2021-03-03 20:27:31 +00:00
Jessica Clarke
9dc27542f3
Use order-only prerequisites for directories
...
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
2021-02-28 04:14:54 +00:00
Peter Rugg
53eb073fb2
Don't track generated Verilog
2021-02-19 19:45:00 +00:00
Peter Rugg
47c94b5a34
Map more RAM in SSITH build
2021-02-19 09:25:41 +00:00
jon
1fbf786294
Add to synthesis file set.
2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7
Add one more missing file and clean up some duplicates.
2021-02-17 18:37:52 +00:00
jon
5ba685b541
Try harder to remove all copies of references to old files.
2021-02-17 16:57:01 +00:00
jon
7a59cad288
Remove more no-longer-generated files from component.xml
2021-02-17 15:54:27 +00:00
jon
059f189bba
Attempt to add all current source files to componenet.xml.
2021-02-17 14:35:49 +00:00
Alexandre Joannou
4c19a34eda
Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57)
2021-02-15 18:07:08 +00:00
Jessica Clarke
fb5339e9ca
Adapt the PLIC instantiation and wiring to support multiple cores
2021-01-31 17:54:43 +00:00
Peter Rugg
f800cdeb77
Prevent spurious warnings
2021-01-30 15:21:38 +00:00
Peter Rugg
e8487e2a1c
Revert "Provide opt-in wedge debugging info"
...
This reverts commit 68d3bd484e
2021-01-19 22:00:16 +00:00
Jessica Clarke
6c98dcb3d8
src_SSITH_P3: Delete stray file references
...
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
2021-01-13 00:59:46 +00:00
Jessica Clarke
1fb31bb255
src_SSITH_P3: Another open-source bsc fix
2021-01-11 21:34:11 +00:00
Jessica Clarke
7ae8689ce5
src_SSITH_P3: Fix build with open-source bsc
...
bsc-contrib puts these under AMBA_TLM3.
2021-01-11 20:57:50 +00:00
