Cheri-research/Toooba
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Commit Graph

556 Commits

Author SHA1 Message Date
Karlis Susters
54b9f6669e Bugfix for L1LL D prefetchers, config for L1LL D Stride-3 2023-03-08 13:37:04 +00:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Karlis Susters
a52a36e199 Push config for L1LL I Single window-2 prefetcher 2023-03-02 15:42:37 +00:00
Karlis Susters
1d2affc707 Set up config for L1I single window-2 prefetcher 2023-03-01 17:20:19 +00:00
Peter Rugg
2047a85b27 Fixes for the simplified debug unit DMA port 2023-02-28 14:55:20 +00:00
Jonathan Woodruff
f255193841 Vastly simplified DMA Connect that does not buffer data at all. 
This has not been tested yet, but it builds.
 2023-02-28 13:28:29 +00:00
Karlis Susters
6509cf6445 Changed config to L1D Block-1 prefetcher and fixed potential bug 2023-02-28 12:29:38 +00:00
Karlis Susters
e228854d9f Change config to next-1-line L1I prefetcher 2023-02-22 17:08:48 +00:00
Jonathan Woodruff
a91f15d10c Merge branch 'CHERI' into jdw57-512axi 2023-02-21 12:18:02 +00:00
Karlis Susters
87a88a749b Set up config for next-2-lines on miss L1I prefetcher 2023-02-21 10:45:56 +00:00
Karlis Susters
bd2ceec15f L1D prefetch into S, not M 2023-02-20 11:17:59 +00:00
Peter Rugg
e981b7625f Ban illegal JALR and Br encodings 2023-02-16 16:41:39 +00:00
Karlis Susters
2c9428d1f3 Prepared repo for building on FPGA 2023-02-13 21:52:50 +00:00
Karlis Susters
9d027a3f4b Implemented BRAM versions of stride, target, markov prefetchers 2023-02-13 11:59:26 +00:00
Karlis Susters
31ae938e78 Implemented a stride prefetcher with BRAM instead of vectors 2023-02-13 11:59:26 +00:00
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
dca4b980c5 Implemented a markov chain data prefetcher 2023-02-13 11:59:26 +00:00
Karlis Susters
9f733eddf1 Merged reportHit & reportMiss, changed compile time parameter passing 2023-02-13 11:59:26 +00:00
Karlis Susters
06e648df6a Implemented target table module, refactored single and multi window instruction prefetchers to use it 2023-02-13 11:59:26 +00:00
Karlis Susters
7c05ebbd90 Implemented multi line target prefetcher 2023-02-13 11:59:26 +00:00
Karlis Susters
e602d4780e LLC prefetcher fixes and single window target prefetcher implementation 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Peter Rugg
8ea0e07ce5 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-02-10 18:12:08 +00:00
Peter Rugg
6931201a14 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-01-31 21:02:17 +00:00
Peter Rugg
9f24a516e6 Remove traps from CSeal and CCSeal 2023-01-16 10:43:32 +00:00
Peter Rugg
ecdc2e0107 Remove remaining unsealed checks 2023-01-11 17:50:37 +00:00
Peter Rugg
4c166c95b9 Change treatment of reserved types in CCopyType 2023-01-11 17:40:51 +00:00
Alexandre Joannou
98e15acb3d Bump BlueStuff + use _Periph versions of parameters where needed 2022-11-18 12:07:24 +00:00
Jonathan Woodruff
4af4b647b1 Merge branch 'CHERI' into jdw57-512axi 2022-11-14 14:51:54 +00:00
Peter Rugg
e120b3427d Merge branch 'LoadTagsImprove' into CHERI 2022-11-14 13:28:44 +00:00
Jonathan Woodruff
ddf4afaf71 Changes to build with a 512-bit main data bus (with all other busses 
still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
 2022-11-11 17:52:32 +00:00
Peter Rugg
de0c0315f4 Remove trap conditions for CCopyType 2022-10-25 22:11:58 +01:00
Peter Rugg
b0233a01c4 Remove trap on CSetBounds* 2022-10-25 22:03:31 +01:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Peter Rugg
2b471b0196 Don't require permit_x when constructing sentries 2022-10-18 15:51:52 +01:00
Peter Rugg
04ba0cb7ab Prefer tag clearing to trapping when manipulating a sealed capability 
This causes the behaviour of CCSeal and CSeal to diverge in non-trapping cases,
meaning an extra case is added to CapModify.
 2022-10-18 15:48:35 +01:00
Alexandre Joannou
d068df3bd8 uncomment a verbosity check 2022-09-02 12:37:07 +00:00
Jonathan Woodruff
1fceb8fa72 Use standard imports as the fixes have been upstreamed. 2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b NonPipelined API update 2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38 Use NonPipelined dividers + update "reset_by" in CoreW 2022-08-15 16:18:23 +00:00
gameboo
45135a0bee Don't assume a XILINX tool flow 2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c Fixes for load address tracing. 2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4 commented out debug print statements in Ras.bsv 2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d added typedefs to STLPred 2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90 removed unnecessary declarations in RenameStage 2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0 Fix tracing of writes to MMIO addresses. 2022-07-22 15:37:25 +00:00
Franz Fuchs
502e64c24b fixed not defined warning in ConnectalBramFifo 2022-07-11 15:11:59 +01:00
Franz Fuchs
4abf838d62 implemented missing notFull method in SpecFifo 2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d used RVFI defines as declared in ToReorderBuffer 2022-07-11 14:18:19 +01:00