Jonathan Woodruff
3908c5f955
A merge resolution not included in previous commit due to not saving file.
...
Doh.
2021-11-02 18:12:05 +00:00
Jonathan Woodruff
7437c0c5e7
Some cleanups.
2021-11-02 18:09:06 +00:00
Franz Fuchs
56173bf2c2
Added interrupt counter
2021-11-02 15:48:02 +00:00
Jessica Clarke
fb1a629e07
Decode: Fix capability width mode-dependent LR/SC
...
All of St, Amo, Lr and Sc use the normal 3-bit encoding for the width;
rather than add Lr and Sc to the list, switch it just to exclude Ld as
the special case that's handled by the other half of the expression.
Previously LR.C and SC.C were decoded as LR.BU and SC.BU.
2021-10-27 15:44:23 +01:00
Alexandre Joannou
1930025e1f
Add StatCounters and GenerateHPMVector dependencies to verilator makefile
2021-10-13 14:50:21 +01:00
Jonathan Woodruff
3d0aee0af4
Remove some verbosity from the committed state.
2021-10-07 16:30:32 +00:00
Jonathan Woodruff
81a12b89cb
Move to NonPipelinedSquareRooter to hopefully fit more
...
deterministically.
We're still waiting for a fixed NonPipelinedDivider.
2021-10-07 16:28:57 +00:00
Franz Fuchs
db54d27368
Move import DReg::* into ifdefs
2021-10-01 16:54:17 +01:00
Franz Fuchs
df74a71d61
changed _Synth to _Sig following the new convention in BlueStuff
2021-09-30 15:02:47 +01:00
Franz Fuchs
b4fe3ee93c
adjusted SSITH_P3 Makefile to new version of HPM Events
2021-09-30 13:33:26 +01:00
gameboo
9657339d87
"fix" non PERFORMANCE_MONITORING build
2021-09-29 18:09:06 +01:00
Franz Fuchs
87977461a6
Merge branch 'CHERI' of github.com:CTSRD-CHERI/Toooba into CHERI
2021-09-29 14:23:20 +01:00
Franz Fuchs
cf8bfdc4a8
Merge branch 'faf28_hpm_consistency' into CHERI
2021-09-29 14:04:08 +01:00
Jonathan Woodruff
c379a7a293
Changes to build with the new stat counters.
2021-09-24 13:18:55 +00:00
Franz Fuchs
db9b5c7f54
re-integrated TagController
2021-09-24 11:39:23 +01:00
Peter Rugg
8ef44b0a6c
Workaround single step wedges by not waiting for flush before halting
2021-09-24 10:33:58 +00:00
Franz Fuchs
4cfac08bca
Bumped BlueStuff and made necessary adaptations
2021-09-23 15:25:46 +01:00
Franz Fuchs
4c194d4e82
integrated new version of RISCV_HPM_Events done by Jess
2021-09-23 14:36:50 +01:00
Franz Fuchs
9ea66bed86
Merge pull request #18 from CTSRD-CHERI/faf28_hpm_consistency
...
Using HPM information from one central struct
2021-09-20 13:21:52 +01:00
Franz Fuchs
d80bc24bf3
Bumped TagController
2021-09-20 11:59:32 +01:00
Franz Fuchs
9320e53720
Bumped RISCV_HPM_Events made minor changes
2021-09-17 10:38:48 +01:00
Franz Fuchs
01000dba56
bump RISCV_HPM_Events
2021-09-14 11:32:45 +01:00
Franz Fuchs
e675400ab8
Fixed things as pointed out by aj443
2021-09-13 16:35:23 +01:00
Franz Fuchs
726c9f19a9
put deprecate note on Performance_Monitoring.md
2021-09-08 16:47:34 +01:00
Jonathan Woodruff
c489a177d4
Fix type error.
2021-09-08 10:23:29 -05:00
Jonathan Woodruff
08231b7e5c
Hopefully don't wedge on ifetch bus error.
...
We think that we were wedging on IFetch bus error.
It appears that we didn't make the last instruction fragment valid in the bus error case, and expect that this path was not previously exercised.
This change returns 0s (to hopefully make the error less subtle) in exactly the right number of fragments.
2021-09-08 10:11:25 -05:00
Franz Fuchs
5d021e8c2e
Bump RISCV_HPM_Events
2021-09-08 12:29:07 +01:00
Franz Fuchs
c3775b80c9
Bumped new version of RISCV_HPM_Events
2021-09-07 16:38:30 +01:00
Franz Fuchs
b567db8e8e
Updated RISCV_HPM_Events submodule
2021-09-07 11:16:40 +01:00
Franz Fuchs
f89e3d79c7
Bumped RISCV_HPM_Events
2021-09-07 08:32:34 +01:00
Franz Fuchs
b25d70a8cc
performed corrections for CONTRACTS_VERIFY
2021-09-07 08:15:03 +01:00
Franz Fuchs
e58000c82d
added HPM Events submodule again
2021-09-06 16:39:25 +01:00
Franz Fuchs
c3648b82c3
Removed submodule HPM Events temporarily
2021-09-06 16:34:38 +01:00
Franz Fuchs
ec1e29c513
Bump HPM Events
2021-09-06 16:01:32 +01:00
Franz Fuchs
bc7eed67ab
Did more cleaning up
2021-09-06 15:55:28 +01:00
Franz Fuchs
4c9d89e936
Performed a bit of cleaning up
2021-09-06 13:33:13 +01:00
Franz Fuchs
0d42b6075a
Bump new HPM Events submodule
2021-09-06 13:10:38 +01:00
Franz Fuchs
e4b4becea4
Added HPM Events submodule
2021-09-06 13:03:18 +01:00
Franz Fuchs
83172e612c
Added makefile support for HPM events files
2021-09-06 12:44:29 +01:00
Franz Fuchs
e33b4021d8
Integrated generateHPMVector function
2021-09-03 17:37:43 +01:00
Franz Fuchs
61d788ebc7
define No_Of_Evts in StatCounters
2021-09-03 14:14:32 +01:00
Franz Fuchs
d36a129bf9
Bump TagController
2021-09-03 08:12:33 +01:00
Franz Fuchs
20e67971a5
Use type EventsCacheCore instead of Vector#(7, Bit#(1))
2021-09-02 16:10:55 +01:00
Franz Fuchs
b490cbb414
Bump TagController
2021-09-02 15:01:10 +01:00
Franz Fuchs
9f615e4481
initial changes for HPM consistency
2021-09-02 14:50:17 +01:00
Robert Norton
0970951184
Fix decoding of lr / sc with explicit bounds.
...
When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register.
2021-09-01 10:16:49 +01:00
Peter Rugg
dbb6043760
Don't compile SelfInv* without define
2021-08-16 14:42:59 +01:00
Robert Norton
7e2a946c4c
Fix incorrect check for permitStoreLocalCap in capChecksMem.
...
The check was missing a NOT and was actually checking for permitStoreGlobalCap.
2021-08-05 12:19:50 +01:00
Robert Norton
5b23f4cea0
Fix incorrect checks in capChecksMem.
...
These checks were broken in several ways:
1) a missing 'else' inverted the priority of PermitStoreViolation vs. PermitStore[Local]Cap exceptions
2) another missing 'else' inverted the priority of PermitStoreCap and PermitStoreLocalCap exceptions
3) No store checks were performed when mem_func == Amo because of the preceding if clause for loads
I decided to flatten the nested if statements by pulling out the conditions into boolean local variables. Hopefully this makes it clearer (as well as fixing the bugs).
2021-08-05 09:33:52 +01:00
Robert Norton
b811cdb967
Remove unnecessary bzero in elf_to_hex.
...
This was causing excessive physical memory usage when running tests in parallel resulting in out-of-memory killer being invoked.
2021-08-02 15:54:29 +01:00
