Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
517 Commits 7 Branches 0 Tags
39e895ca4ed988042fccbca2844101da3fe8e1e6
Commit Graph

517 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Franz Fuchs
39e895ca4e added documentation of hardware performance monitoring events 
This document lists all implemented events and gives a short explanation
of what counting these events means.
 2021-03-04 16:45:02 +01:00
jon
6ea387f744 Fix performance bug in PC compression where we execute across a page 
boundary.
 2021-03-04 14:41:50 +00:00
Peter Rugg
0e1e2249a6 Default to dual-core builds 2021-03-04 11:54:35 +00:00
Jonathan Woodruff
db08e96596 Add Btb to the component.xml. 2021-03-03 20:27:31 +00:00
Peter Rugg
7a1d234e40 Merge branch 'ifetch-cleanup' into CHERI 2021-03-02 11:57:31 +00:00
Jessica Clarke
9dc27542f3 Use order-only prerequisites for directories 
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
 2021-02-28 04:14:54 +00:00
Jessica Clarke
e1060ac43d TlbTypes: Fix exception code reported for some store page fault conditions 
The mode and well-formedness checks above also set fault to True, so we
end up with cases where a DataStore request uses the default load page
fault exception code. Instead, unconditionally set excStorePageFault for
DataStore, and conditionally override to excStoreCapPageFault when
appropriate, being particularly careful to ensure earlier exception
causes still take precedence.

Also restructure the InstFetch and DataLoad cases to match how DataStore
needs to look.

This fixes the rv64si-p-dirty ISA test, currently the sole failure.
 2021-02-28 03:51:05 +00:00
Jessica Clarke
c7bd60b47e CSRs: Don't guard HPM CSRs with PERFORMANCE_MONITORING 
They always exist, just WARL so can be hard-wired.
 2021-02-28 01:11:39 +00:00
jon
9d5095b076 Count CJALRs with Jrs. 2021-02-24 20:36:46 +00:00
Jessica Clarke
df430e22c8 Exec: Enable non-ASR access to TIME 
This is needed for benchmarking.
 2021-02-24 04:17:42 +00:00
Jessica Clarke
7776bac8b5 Exec: Enable non-ASR access to HPMCOUNTERn 
These are now defined, and needed for benchmarking.
 2021-02-23 20:35:18 +00:00
Peter Rugg
5b6e8d88f6 Add CSetEqualExact 2021-02-22 17:44:36 +00:00
Peter Rugg
53eb073fb2 Don't track generated Verilog 2021-02-19 19:45:00 +00:00
jon
2f0b0c110f Use the necessary number of ports. 2021-02-19 17:38:16 +00:00
jon
b5bce1209a Revert "Revert biggest scheduling change from potentially problematic commit." 
This one does not actually build with the new BSC compiler.  I forgot to
test the hardware build (with GDB), which is where we have the problem.
This reverts commit b4308e9a6e.
 2021-02-19 17:38:16 +00:00
Peter Rugg
9f0968b1cb Fix AXI_Size=16 for MMIO of caps 2021-02-19 17:19:47 +00:00
Peter Rugg
47c94b5a34 Map more RAM in SSITH build 2021-02-19 09:25:41 +00:00
jon
b4308e9a6e Revert biggest scheduling change from potentially problematic commit. 
This still builds with the new BSC compile.
 2021-02-18 15:18:58 +00:00
jon
1fbf786294 Add to synthesis file set. 2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7 Add one more missing file and clean up some duplicates. 2021-02-17 18:37:52 +00:00
jon
0f3fd15d41 Initial implementation of map of HPM counters into supervisor and user 
mode.  This version just unconditionally exposes them.
 2021-02-17 17:07:53 +00:00
jon
5ba685b541 Try harder to remove all copies of references to old files. 2021-02-17 16:57:01 +00:00
jon
7a59cad288 Remove more no-longer-generated files from component.xml 2021-02-17 15:54:27 +00:00
jon
9d2acbd96d Bump to latest version of Bluestuff. 2021-02-17 14:59:31 +00:00
jon
059f189bba Attempt to add all current source files to componenet.xml. 2021-02-17 14:35:49 +00:00
Alexandre Joannou
4c19a34eda Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57) 2021-02-15 18:07:08 +00:00
Marno van der Maas
e3b776a81f Clarified supported versions of verilator 2021-02-12 09:49:17 +00:00
jon
9e36ff95cd Roll back accidental commit of experimental change. 2021-02-11 12:22:00 +00:00
jon
96be5802a0 Bump BlueStuff with workaround. 2021-02-10 17:23:46 +00:00
jon
40ea082310 Some updates to build with the new bsc compiler. 2021-02-10 17:22:26 +00:00
jon
9dd2dd9c77 Bump cheri-cap-lib. 2021-02-10 17:22:26 +00:00
Marno
65d0edd722 Bump BlueStuff to fix compiler error with new bsc 2021-02-10 14:07:02 +00:00
Peter Rugg
a78d09c522 Add ifdefs for GDB control on helper functions 2021-02-08 14:49:13 +00:00
Jessica Clarke
fb5339e9ca Adapt the PLIC instantiation and wiring to support multiple cores 2021-01-31 17:54:43 +00:00
Peter Rugg
cedb4c279d Ensure the MMIO platform issues aligned requests by changing the AXI4_Size field based on the byte enables 2021-01-31 17:34:35 +00:00
Peter Rugg
44e19afbf3 Fix MMIO bug missing uncached instruction bytes with certain alignments 2021-01-30 15:22:22 +00:00
Peter Rugg
f800cdeb77 Prevent spurious warnings 2021-01-30 15:21:38 +00:00
Peter Rugg
d340066f6f Multicore debug cleanups 2021-01-21 20:51:02 +00:00
Peter Rugg
30e7090213 Multicore debug-module 2021-01-21 20:30:07 +00:00
Peter Rugg
3417fb454e Revert "Provide opt-in wedge debugging info" - some missed changes 
This reverts commit 68d3bd484e.
 2021-01-21 20:30:07 +00:00
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs" 
This reverts commit 5e9b478371.
 2021-01-19 21:39:59 +00:00
jon
c515fb4518 Remove commented-out code. 
Enable building with open-source BSC.

Resolve a couple issues brought up by Jess.

Remove a stray space (as noted by Jess).
 2021-01-14 17:10:04 +00:00
jon
a6771219ba Fold the fragment count into the standard pipeline structs. 2021-01-14 12:29:38 +00:00
jon
fc968c867f PC compression scheme for the instruction fetch pipeline. 
Store the upper bits of the PC in a table and only handle indices and
lsbs in the main pipeline.
This eliminates redundancy between PCs and predicted PCs, and even more
between fragments of instructions.
 2021-01-14 11:41:11 +00:00
jon
dd82b2703c Record an exception from either half of an instruction, with preference 
for the first half.
 2021-01-13 15:33:08 +00:00
jon
0d93ed3ad2 Merge branch 'CHERI' into ifetch-cleanup 2021-01-13 15:21:20 +00:00
Jessica Clarke
6c98dcb3d8 src_SSITH_P3: Delete stray file references 
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
 2021-01-13 00:59:46 +00:00
Jessica Clarke
1fb31bb255 src_SSITH_P3: Another open-source bsc fix 2021-01-11 21:34:11 +00:00