gameboo
47e12b8e65
Revert "Use only 20 bits of address on the AXI lite port"
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This reverts commit c766187368
2024-09-11 20:02:35 +01:00
gameboo
c766187368
Use only 20 bits of address on the AXI lite port
2024-07-08 17:12:47 +01:00
Jonathan Woodruff
271bc9c0e8
Experimentally remove deburster.
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This thing has a seraliser in it that serialises memory accesses, which
is a disaster for performance.
2024-02-16 09:50:07 +00:00
gameboo
afba99d0a1
Added missing DefaultValue import
2023-05-17 17:50:05 +01:00
Jonathan Woodruff
a38610869d
Merge branch 'jdw57-512axi' of https://github.com/CTSRD-CHERI/Toooba into jdw57-512axi
2023-02-28 13:27:10 +00:00
gameboo
aa68739ab6
Update imports in CoreW
2023-02-23 14:51:24 +00:00
Jonathan Woodruff
a91f15d10c
Merge branch 'CHERI' into jdw57-512axi
2023-02-21 12:18:02 +00:00
Peter Rugg
50c51e93a1
Add assertion that ndm resets don't get dropped
2023-02-09 14:34:13 +00:00
Jonathan Woodruff
e73d8223ea
Use working tag controller (at 512-bits wide, so quite wasteful for
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now...).
2022-11-23 10:25:48 +00:00
Jonathan Woodruff
e9d7b85b63
Use working tag controller; merge with more explicit types.
2022-11-23 10:22:04 +00:00
Alexandre Joannou
98e15acb3d
Bump BlueStuff + use _Periph versions of parameters where needed
2022-11-18 12:07:24 +00:00
Jonathan Woodruff
4af4b647b1
Merge branch 'CHERI' into jdw57-512axi
2022-11-14 14:51:54 +00:00
Jonathan Woodruff
01482abb1b
Move to new name for null tag controller.
2022-11-14 13:48:21 +00:00
Peter Rugg
e120b3427d
Merge branch 'LoadTagsImprove' into CHERI
2022-11-14 13:28:44 +00:00
Jonathan Woodruff
ddf4afaf71
Changes to build with a 512-bit main data bus (with all other busses
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still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
2022-11-11 17:52:32 +00:00
Jonathan Woodruff
066289f8aa
Work in progress.
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Wd_Data is moved to 512 bits, and LLC_AXI4_Adapter is updated.
Lots of build errors now; a few have been resolved.
2022-11-10 13:51:12 +00:00
Alexandre Joannou
54456b5f50
Fix the non-rvfi_dii build
2022-10-21 09:50:49 +00:00
Jonathan Woodruff
0562cb18a1
Fix for RVFI_DII build.
2022-10-21 09:18:28 +00:00
Alexandre Joannou
02ba37bf6a
Report the actual running state to the debug module
2022-09-08 13:20:35 +00:00
Alexandre Joannou
a0d471e4f8
Attempt to make toHost setiing behave in src_Testbench
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Made the proc start method non-blocking on mmio platform and wired in a new way
to set the tohost addr using a control and status request, and bumpped
WindCoreInterface accordingly
2022-09-06 10:42:34 +00:00
Alexandre Joannou
2240c87c78
Fix src_Testbench toplevel build for tests and bump BlueStuff
2022-08-25 15:25:55 +00:00
Alexandre Joannou
5bf15adf04
Addressed @francislaus comments
2022-08-17 08:41:27 +00:00
gameboo
6b51139c9a
Update ack
2022-08-15 16:18:23 +00:00
Alexandre Joannou
47930189da
Bump BlueStuff + assume external subordinate_0 parameters that match internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a
Bump BlueStuff + add outter subordinate trafic as master to internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
bb62b703c8
Address some rebase nonsense
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a65c93ee98
Update resetting in coreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
2c450aea8c
Some reset adjustments
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38
Use NonPipelined dividers + update "reset_by" in CoreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
b32da9034b
Fix addr to DM_addr convertion (pointed out by jrtc27)
2022-08-15 16:18:23 +00:00
gameboo
72320b32b2
Update to AXI lite for debug module port
2022-08-15 16:18:23 +00:00
gameboo
b9ee27f390
Update to WindCoreMid + Bump WindCoreInterface
2022-08-15 16:18:23 +00:00
gameboo
812c961360
Introduce the WindCoreInterface
2022-08-15 16:18:23 +00:00
Peter Rugg
6d4644ce73
Add tag-only state to MESI and interface with tagOnlyReq of tag controller
2022-03-31 02:07:01 +01:00
Jonathan Woodruff
6ea5d34d06
Bump Bluestuff.
2022-01-25 17:05:34 +00:00
gameboo
9657339d87
"fix" non PERFORMANCE_MONITORING build
2021-09-29 18:09:06 +01:00
Franz Fuchs
db9b5c7f54
re-integrated TagController
2021-09-24 11:39:23 +01:00
Franz Fuchs
4cfac08bca
Bumped BlueStuff and made necessary adaptations
2021-09-23 15:25:46 +01:00
Franz Fuchs
20e67971a5
Use type EventsCacheCore instead of Vector#(7, Bit#(1))
2021-09-02 16:10:55 +01:00
jon
d7a492b48f
Move to Flute standard placement for Tag Cache events, which is just the
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raw order from the CacheCore events.
2021-06-01 15:17:25 +01:00
Jessica Clarke
fb5339e9ca
Adapt the PLIC instantiation and wiring to support multiple cores
2021-01-31 17:54:43 +00:00
Peter Rugg
d340066f6f
Multicore debug cleanups
2021-01-21 20:51:02 +00:00
Peter Rugg
30e7090213
Multicore debug-module
2021-01-21 20:30:07 +00:00
Peter Rugg
e8487e2a1c
Revert "Provide opt-in wedge debugging info"
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This reverts commit 68d3bd484e
2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587
Revert "Plumb through a lot more ROB debug state"
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This reverts commit 0f65994955
2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d
Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs"
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This reverts commit 5e9b478371
2021-01-19 21:39:59 +00:00
jon
bab989d6d2
Support for stat counters from the tag controller.
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The order of the events is very not tested; 50% chance of being correct.
2020-12-17 12:38:52 +00:00
jon
3f60c046f7
Fix typo.
2020-12-04 16:51:44 +00:00
Alexandre Joannou
98a9c076cd
Update BlueStuff API and Bump BlueStuff and TagController
2020-12-01 14:22:12 +00:00
Jessica Clarke
0516db5e8d
Bump BSV-RVFI-DII and refactor to support new parcel-based interface
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This means FetchStage should now behave in the same way with RVFI-DII as
with an I-Cache. A Dii_Parcel_Id is fed alongside PC everywhere relevant
and follows very similar logic, but, importantly it's just extra state
on the side, it doesn't affect what we do with the branch predictor and
parcel combining/instruction decoding logic.
2020-07-21 14:36:36 +01:00
