Cheri-research/Toooba
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Author SHA1 Message Date
jon
bab989d6d2 Support for stat counters from the tag controller. 
The order of the events is very not tested; 50% chance of being correct.
 2020-12-17 12:38:52 +00:00
jon
4131dcd073 Cause two surprising conditions to not throw slave errors as this is not 
specified and causes kernel panics.  Hopefully the details of what
should happen in these cases is correct, but we shall see...
 2020-12-17 12:37:45 +00:00
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
17a7a32092 Use DRegOR instead of immitating latching behaviour. 2020-12-15 16:18:36 +00:00
jon
d64df09d82 Bump to version with DRegOR. 2020-12-15 16:18:18 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
jon
982758cae7 Bump to version of Bluestuff that has the saturating truncate function. 2020-12-14 12:13:34 +00:00
Jessica Clarke
f6569e2d14 Actually do the intended fix, not just inverting the variable 2020-12-14 10:51:57 +00:00
Jessica Clarke
295b878836 Fix negated CYCLE/INSTRET logic for ASR and make less confusing 2020-12-14 10:50:23 +00:00
jon
6768bf92c7 iMove the store count to the pipeline write. 
It appeared to be counting capabilities in store counter flushes, which,
FI think, is not quite what was intended in this counter.
 2020-12-11 17:16:38 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
bdc2d494f2 Change name something that makes sense. 2020-12-04 17:12:26 +00:00
jon
3f60c046f7 Fix typo. 2020-12-04 16:51:44 +00:00
jon
f42c3f3577 Merge branch 'cheri-perfmon' into CHERI 2020-12-04 16:29:51 +00:00
jon
5665d2e9cd A more effective Fence count (as some fences go through as the Nop 
iType).
 2020-12-04 16:28:19 +00:00
jon
425c2778c0 Bump Bluestuff to get resetting in the Performance Monitor. 2020-12-03 17:55:03 +00:00
jon
1fb388fb18 Count more things correctly. 2020-12-03 17:54:46 +00:00
jon
8a13b866d7 Bump bluestuff to the one with generalised report width. 2020-12-02 15:31:49 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
742c4c5c92 Bump Bluestuff. 2020-12-01 18:03:44 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Peter Rugg
bf77ac74ba Fix performance reporting requests for multicore 2020-11-04 12:11:31 +00:00
Peter Rugg
61b88ef987 Generate elf files the correct size 2020-11-02 11:23:07 +00:00
Marno van der Maas
328592b068 Added missing slash in readme 2020-10-29 15:45:17 +00:00
PeterRugg
844bfd5e79 Merge pull request #5 from nwf/capdirty 
Add CHERI PTE CapDirty flag
 2020-10-02 17:17:24 +01:00
Marno van der Maas
ed9541e8d0 Put all dirs for source description in code blocks 2020-10-02 13:09:51 +01:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00
jon
00ffdd7228 Enable to build with latest BSC compiler. 2020-08-11 14:46:28 +01:00
jon
8896bb27f1 Revert "Remove the special flush from the Fetch3 stage." 
This reverts commit 4fe24c9cd5.
 2020-07-29 11:40:00 +01:00
jon
4fe24c9cd5 Remove the special flush from the Fetch3 stage. 
This is an intermediate simplification for moving to SupFifo-based picking.
 2020-07-29 07:40:15 +01:00
Peter Rugg
3132f9f55f Trap when writing PCC, rather than silently ignoring 2020-07-28 12:57:13 +01:00
Jessica Clarke
73dedec309 FetchStage: Use map rather than for loop 
Also add some spaces in the following line.
 2020-07-24 20:02:10 +01:00
Jessica Clarke
0b3ad23c24 Fix typo 2020-07-24 19:10:11 +01:00
Jessica Clarke
1bad5b080b Various updates to README.md 
* Fix the arch string
 * Document the RVFI-DII build directories
 * Don't tell people to build RTL using them
 * Bluesim build configurations exist
 2020-07-24 19:06:56 +01:00
Jessica Clarke
44d49a52c0 Drop removed CHERI directory from README.md (Closes: #3) 
27947f4df7 moved the SCRs into the main
CSR register file, and that was the only thing in this directory.
 2020-07-24 18:47:26 +01:00
jon
40af067a71 Fix RVFI_DII build in the presence of 2-byte bundles. 2020-07-24 17:30:29 +01:00
jon
1f968b0c07 2-byte aligned instruction memory to simplify compressed instruction 
fetch.
 2020-07-24 12:38:37 +01:00
Peter Rugg
ecce475b97 Merge branch 'mem_perm_checks' into CHERI 2020-07-23 16:53:14 +01:00
Peter Rugg
27082ee2a9 Report writes to PCC as illegal instruction, not ASR violation 2020-07-23 15:40:28 +01:00
Peter Rugg
97d89086a6 Bump cheri-cap-lib 2020-07-23 11:20:30 +01:00
Peter Rugg
e8aa873c2e Prevent 'insufficient type info' warning 2020-07-23 11:18:31 +01:00
Peter Rugg
a6b40e946b Prevent using CCSeal to 'seal over' other types 2020-07-23 11:18:07 +01:00
Peter Rugg
c693462f6b Add tag-clearing due to cap load perm and PTE bits 2020-07-22 15:54:49 +01:00