Cheri-research/Toooba
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cb1858447be3e6fcbb7a5c2442ca6d0cdd35ba42
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365 Commits

Author SHA1 Message Date
Jonathan Woodruff
cb1858447b Fix tracing of Sc. 
Sc is unique in that it writes both memory and a register value.
This implementation works around the fact that the memory store data and
the register write data are sharing the same field in the reorder buffer
by inferring the writeback value of Sc from the byteEnable field.
 2021-11-03 12:45:15 +00:00
Jonathan Woodruff
3908c5f955 A merge resolution not included in previous commit due to not saving file. 
Doh.
 2021-11-02 18:12:05 +00:00
Jonathan Woodruff
7437c0c5e7 Some cleanups. 2021-11-02 18:09:06 +00:00
Franz Fuchs
56173bf2c2 Added interrupt counter 2021-11-02 15:48:02 +00:00
Jessica Clarke
fb1a629e07 Decode: Fix capability width mode-dependent LR/SC 
All of St, Amo, Lr and Sc use the normal 3-bit encoding for the width;
rather than add Lr and Sc to the list, switch it just to exclude Ld as
the special case that's handled by the other half of the expression.

Previously LR.C and SC.C were decoded as LR.BU and SC.BU.
 2021-10-27 15:44:23 +01:00
Jonathan Woodruff
3d0aee0af4 Remove some verbosity from the committed state. 2021-10-07 16:30:32 +00:00
Jonathan Woodruff
81a12b89cb Move to NonPipelinedSquareRooter to hopefully fit more 
deterministically.
We're still waiting for a fixed NonPipelinedDivider.
 2021-10-07 16:28:57 +00:00
Franz Fuchs
db54d27368 Move import DReg::* into ifdefs 2021-10-01 16:54:17 +01:00
gameboo
9657339d87 "fix" non PERFORMANCE_MONITORING build 2021-09-29 18:09:06 +01:00
Franz Fuchs
b25d70a8cc performed corrections for CONTRACTS_VERIFY 2021-09-07 08:15:03 +01:00
Franz Fuchs
bc7eed67ab Did more cleaning up 2021-09-06 15:55:28 +01:00
Franz Fuchs
e33b4021d8 Integrated generateHPMVector function 2021-09-03 17:37:43 +01:00
Franz Fuchs
61d788ebc7 define No_Of_Evts in StatCounters 2021-09-03 14:14:32 +01:00
Franz Fuchs
9f615e4481 initial changes for HPM consistency 2021-09-02 14:50:17 +01:00
Robert Norton
0970951184 Fix decoding of lr / sc with explicit bounds. 
When decoding {lr,sc}.{b,h,w,d,c,q}.{ddc,cap} the IType was not being set correctly. For sc we also need to set the destination register.
 2021-09-01 10:16:49 +01:00
Robert Norton
7e2a946c4c Fix incorrect check for permitStoreLocalCap in capChecksMem. 
The check was missing a NOT and was actually checking for permitStoreGlobalCap.
 2021-08-05 12:19:50 +01:00
Robert Norton
5b23f4cea0 Fix incorrect checks in capChecksMem. 
These checks were broken in several ways:

1) a missing 'else' inverted the priority of PermitStoreViolation vs. PermitStore[Local]Cap exceptions
2) another missing 'else' inverted the priority of PermitStoreCap and PermitStoreLocalCap exceptions
3) No store checks were performed when mem_func == Amo because of the preceding if clause for loads

I decided to flatten the nested if statements by pulling out the conditions into boolean local variables. Hopefully this makes it clearer (as well as fixing the bugs).
 2021-08-05 09:33:52 +01:00
Franz Fuchs
cc25ee69d3 Check in Rename stage for nextPcs of Traps 2021-07-26 07:02:21 +01:00
Franz Fuchs
483cef8852 Removed unnecessary display statements 2021-07-12 14:55:07 +02:00
Franz Fuchs
7b1b564d62 Added missing ifdef 2021-07-12 13:30:53 +01:00
Franz Fuchs
c37c611522 Merge branch 'CHERI' into faf28_sbc_jumps 2021-07-08 17:14:27 +01:00
Franz Fuchs
224ab35679 Completed introduction of new build flag 2021-07-08 15:38:19 +01:00
Franz Fuchs
4ba377366a Introduced new build flag for transient-execution testing contracts 2021-07-08 15:28:54 +01:00
jon
849d5c57f8 Fix condition where Queue can remain "empty" when there were outstanding 
indices due to the head-1 element happening to match new requests.
This leads to "remove" when empty, leading to being "almostFull" when
there are no outstanding users that will remove anything.
 2021-07-07 11:34:29 +01:00
jon
994321e527 Potential fix for lockup condition where the (undefined) bits of 
instruction returned for an invalid fetch (that is, with a valid cause)
indicate a 2-fragment instruction but where a second fragment is not
available.
 2021-07-07 11:34:29 +01:00
Franz Fuchs
db6a91e0fd mad Maps flush on reset 2021-07-06 15:19:37 +01:00
Franz Fuchs
2eb2202acd Added checking for wild exceptions in MemExePipeline including adding an addtional port to the ROB for reading ppc/orig_inst 2021-06-28 07:34:57 +01:00
jon
b48a161fda Experimentally remove repeated write of rg_m_halt_req register. 2021-06-25 17:31:10 +01:00
Franz Fuchs
fec16f64c8 Added first attempts for counting wild exceptions 2021-06-25 15:44:29 +01:00
Franz Fuchs
f83d7b1554 Added missing ifdefs 2021-06-24 08:35:21 +01:00
Franz Fuchs
0c80ac30bb Corrected wild jumps type to SupCnt 2021-06-23 15:36:45 +01:00
Franz Fuchs
c9df8da1b1 Corrected SBC counting 2021-06-23 12:47:34 +01:00
Franz Fuchs
23913a50e0 Improved code for detecting SBC violations 2021-06-23 08:00:42 +01:00
Franz Fuchs
76cdc13a50 Added counting code for return instructions 2021-06-22 18:01:32 +01:00
Franz Fuchs
8f45238b5d implemented method returning the trans exe events 2021-06-22 08:49:40 +01:00
Franz Fuchs
06e0a3d810 corrected SBC jumps counting 2021-06-22 08:40:27 +01:00
Franz Fuchs
a60bed404a Added new counting for branching instructions 2021-06-11 17:09:21 +01:00
Franz Fuchs
dce934500d Added counter mechanism for wild jumps 2021-06-11 10:47:15 +01:00
Franz Fuchs
c51af07278 Collect all architectural jump targets (the first 16) in a bag to enable verifying properties 2021-06-10 18:55:00 +01:00
Franz Fuchs
2572fdceba Added documentation for rename counter and removed unnecessary display messages 2021-06-08 15:03:12 +01:00
Franz Fuchs
914eb17550 Added microarchitectural counter for renamed instructions 
This counter is used for the SBC Condition 1 verification
 2021-06-08 13:18:57 +01:00
jon
4ae9f5346c Merge branch 'CHERI' of https://github.com/CTSRD-CHERI/Toooba into CHERI 2021-06-01 15:18:29 +01:00
jon
d7a492b48f Move to Flute standard placement for Tag Cache events, which is just the 
raw order from the CacheCore events.
 2021-06-01 15:17:25 +01:00
Peter Rugg
1b5f4ee9e0 Add capability-aware compressed decoding 2021-05-26 16:25:55 +01:00
Peter Rugg
88751cccba Remove hardcoded field encodings for cap loads and stores 2021-05-26 16:25:55 +01:00
Peter Rugg
913d14406e Add explicit PCC and cap JALRs 2021-05-26 16:24:41 +01:00
Peter Rugg
6450d9c33c Make JAL and JALR mode-dependent 2021-05-26 16:24:41 +01:00
Peter Rugg
657124671c Support amoswap.c 2021-05-13 23:15:25 +01:00
Peter Rugg
abc70134b1 Don't take load cap page faults if the authorising cap doesn't have load cap 2021-05-13 23:15:25 +01:00
Peter Rugg
7e77b2314b Clarify precedence in VM permission check 2021-05-05 13:32:07 +01:00