dmactive should only go low when the debug module has successfully
reset. Approximate this by waiting for 1024 cycles, allowing any
register access requests and system bus requests to come back.
This was probably removed for performance, but now that we have
a faster workaround for loading kernels on the DE10, we should
probably prioritise accurate error information instead.
Previously, Makefiles had to add new include paths and -D defines manually when they wanted to include RVFI.
This caused hard-to-diagnose errors in repositories consuming Toooba that expected -D RVFI to work.
This commit makes Include_RISCY_Config.mk take an optional make-variable argument RVFI, which defaults to "false", and adds the relevant paths and -D defines if it is set to "true".
This does not cover RVFI_DII, which is a simulation-only extension to allow instruction injection.
This commit also includes fixes to the Makefiles in ./builds/ to use this interface properly.
Konata: change M to F3
Added konata support to ALU pipeline
Added KONATA support to Fpu pipeline
Added KONATA support to Mem pipeline
Finished v1 of KONATA support
Added improvements to catch fragments in Konata
Kill fragments that have been merged
Fixed order of konata logs
Added commit stage output
Ensured that only the Commit stage can retire instructions in konata
Fixed printing commit stage log for Cap instructions
Changed Kanata to include the cycle counter for each line in the log file; please note that this requires post processing
Added reservation station support for Konata
Added parsing script for Toooba output
Removed double updated to D stage
Adressed Peter's comments
The referenced commit did not merge well with our code base. Therefore, I copied over the changes manually. These changes do
not constitute a working Konata support for Toooba. In this commit, I commented out some things that did not compile, which will be fixed in future
Just use the same ID for all outstanding requests such that all requests
are in-order.
Previously we were working fine with requests serialised; requests
are now fully pipelined and out-of-order.
This change should roll back to in-order, but still pipelined.
This only affects the top-level used in the GFE (vcu118).
This design is working on the DE10 setup, so the issue is not
believed fundamental with CoreW.
use it only in the L1 caches so that the L2 cache can have lower
resource utilisation and better timing. (Resource utilisation is up
about 5% with the new design, and it's not necessary for the L2 cache.)
