Cheri-research/Toooba
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e6a8111a1b6869fb037443f03ffeb69b71f41533
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475 Commits

Author SHA1 Message Date
gameboo
e6a8111a1b Fix forgotten type change from tuple2 to tuple3 in mem exe pipeline 2023-06-14 11:49:09 +01:00
Jonathan Woodruff
f476990c65 Merge branch 'CHERI' into ks980-prefetch 2023-05-17 15:32:40 +00:00
Karlis Susters
5733ed9ac0 Implemented overflow bypass fifo, required for double target table 2023-04-12 21:58:35 +03:00
Karlis Susters
30a3aff5af Config for L1D Stride-3 prefetcher 2023-03-07 12:33:51 +00:00
Peter Rugg
2047a85b27 Fixes for the simplified debug unit DMA port 2023-02-28 14:55:20 +00:00
Jonathan Woodruff
f255193841 Vastly simplified DMA Connect that does not buffer data at all. 
This has not been tested yet, but it builds.
 2023-02-28 13:28:29 +00:00
Jonathan Woodruff
a91f15d10c Merge branch 'CHERI' into jdw57-512axi 2023-02-21 12:18:02 +00:00
Peter Rugg
e981b7625f Ban illegal JALR and Br encodings 2023-02-16 16:41:39 +00:00
Karlis Susters
79c55c5651 Implemented cross cache prefetching, fixed some coherence bugs in LLC 2023-02-13 11:59:26 +00:00
Karlis Susters
347107b733 Prefetcher implementation in both L1 and LL and data logging 2023-02-13 11:59:26 +00:00
Peter Rugg
8ea0e07ce5 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-02-10 18:12:08 +00:00
Peter Rugg
6931201a14 Avoid wedge on repeated debug resumes (with jdw57 and aj443) 
ConfigReg avoids a compile error
 2023-01-31 21:02:17 +00:00
Alexandre Joannou
98e15acb3d Bump BlueStuff + use _Periph versions of parameters where needed 2022-11-18 12:07:24 +00:00
Jonathan Woodruff
4af4b647b1 Merge branch 'CHERI' into jdw57-512axi 2022-11-14 14:51:54 +00:00
Peter Rugg
e120b3427d Merge branch 'LoadTagsImprove' into CHERI 2022-11-14 13:28:44 +00:00
Jonathan Woodruff
ddf4afaf71 Changes to build with a 512-bit main data bus (with all other busses 
still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
 2022-11-11 17:52:32 +00:00
Franz Fuchs
de0e19ca55 added do not cares for missing struct fields in ROB 2022-10-21 09:22:31 +00:00
Alexandre Joannou
d068df3bd8 uncomment a verbosity check 2022-09-02 12:37:07 +00:00
Jonathan Woodruff
1fceb8fa72 Use standard imports as the fixes have been upstreamed. 2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b NonPipelined API update 2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a Bump BlueStuff + add outter subordinate trafic as master to internal bus 2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38 Use NonPipelined dividers + update "reset_by" in CoreW 2022-08-15 16:18:23 +00:00
gameboo
45135a0bee Don't assume a XILINX tool flow 2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c Fixes for load address tracing. 2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4 commented out debug print statements in Ras.bsv 2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d added typedefs to STLPred 2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90 removed unnecessary declarations in RenameStage 2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0 Fix tracing of writes to MMIO addresses. 2022-07-22 15:37:25 +00:00
Franz Fuchs
4abf838d62 implemented missing notFull method in SpecFifo 2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d used RVFI defines as declared in ToReorderBuffer 2022-07-11 14:18:19 +01:00
Alexandre Joannou
9960d67ed8 Removed some debug print statements 2022-07-11 11:55:40 +00:00
Franz Fuchs
c85b13c5af added MELTDOWN_CF ifdef and enabled it 2022-06-30 12:55:53 +01:00
Peter Rugg
fb259583dc Attempt to clear tag on exception path before forwarding. 
This is likely to be bad for timing, but might just work at 25MHz.
 2022-06-15 00:53:55 +01:00
Franz Fuchs
f8b97ceb6a corrected ifdef in STLPred.bsv 2022-06-09 15:24:10 +01:00
Franz Fuchs
b79a228093 added no prediction STL predictor 2022-06-08 12:23:35 +01:00
Franz Fuchs
891567f3aa added STL predictor module and moved state from SplitLSQ to it 2022-06-08 12:04:25 +01:00
Peter Rugg
b113d05095 Prioritise misaligned over RVFIDII load access fault 2022-05-18 14:59:43 +01:00
Franz Fuchs
fd639f4b22 added typedef for static number in Ras.bsv 2022-05-14 17:16:40 +01:00
Peter Rugg
6d4644ce73 Add tag-only state to MESI and interface with tagOnlyReq of tag controller 2022-03-31 02:07:01 +01:00
Jonathan Woodruff
9bfaf4cbf0 Swap poliarity of prediction for comparison with upstream. 2022-03-25 14:03:06 +00:00
Jonathan Woodruff
6d7f95571f Merge remote-tracking branch 'origin/CHERI' into jdw57_prediction 2022-03-25 13:06:22 +00:00
Jonathan Woodruff
3cdc2d31c8 Experimentally increase delay before reset. 2022-03-21 10:13:48 +00:00
Jonathan Woodruff
09db91f8c8 Reset counter if head becomes valid. 2022-03-16 11:39:57 +00:00
Jonathan Woodruff
7b78c0ed7b Delay returns (up to 10 cycles) if there is an outstanding push. 2022-03-14 18:45:34 +00:00
Peter Rugg
a6b39b58a1 Clean up prints 2022-03-11 10:24:39 +00:00
Jonathan Woodruff
37a7745f1a Fix a few errors in the previous commit, and importantly, make the 
"push" from writeback just a write to the location that was meant to
push to, rather than the current head.
 2022-03-10 11:04:54 +00:00
Peter Rugg
a6976c0071 Fix RVFI-only build 2022-03-09 22:18:08 +00:00
Jonathan Woodruff
9d68d877d9 Move to much simpler design. 
Just update the head in Decode, and write data from Execute.
A loop calling from the same place will at least find the correct
address.
Also, the bad fixup interaction is solved.
 2022-03-09 12:32:01 +00:00
Jonathan Woodruff
bbdcf6dde9 A more sophisticated RAS protection delay. 
Saturate down, and also predict with old push value if there is more
than 6 cycles of delay.
 2022-03-08 15:17:54 +00:00
Jonathan Woodruff
064cd22114 Inteligently delay Decode (for up to 8 cycles) if we encounter a pop 
while waiting for a push.
 2022-03-07 17:52:11 +00:00