Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity
461 Commits 7 Branches 0 Tags
e8487e2a1c0e7bf20fcef79ed05f25df2bf9e35d
Commit Graph

461 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Peter Rugg
e8487e2a1c Revert "Provide opt-in wedge debugging info" 
This reverts commit 68d3bd484e.
 2021-01-19 22:00:16 +00:00
Peter Rugg
20f1ddf587 Revert "Plumb through a lot more ROB debug state" 
This reverts commit 0f65994955.
 2021-01-19 21:40:59 +00:00
Peter Rugg
a6ab823d1d Revert "Cover interesting fetch and rename state for DEBUG_WEDGE configs" 
This reverts commit 5e9b478371.
 2021-01-19 21:39:59 +00:00
Jessica Clarke
6c98dcb3d8 src_SSITH_P3: Delete stray file references 
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
 2021-01-13 00:59:46 +00:00
Jessica Clarke
1fb31bb255 src_SSITH_P3: Another open-source bsc fix 2021-01-11 21:34:11 +00:00
Jessica Clarke
7ae8689ce5 src_SSITH_P3: Fix build with open-source bsc 
bsc-contrib puts these under AMBA_TLM3.
 2021-01-11 20:57:50 +00:00
Jessica Clarke
4a0c8fe7d2 PLIC: Update comment after previous commit 2020-12-21 13:37:01 +00:00
Jessica Clarke
ac6244181a PLIC: Allow multiple interrupts to be claimed but not completed 
Whilst the current PLIC spec is hard to decipher, the older v1.9
privileged spec is clearer. The intent is that each interrupt is
independent and so claims and completions can be overlapped (e.g. as
done by FreeBSD if deferring an interrupt handler). This is
approximately expressed in the spec by:

  The PLIC can perform a claim at any time and the claim operation is
  not affected by the setting of the priority threshold register.

  ...

  The PLIC does not check whether the completion ID is the same as the
  last claim ID for that target. If the completion ID does not match an
  interrupt source that is currently enabled for the target, the
  completion is silently ignored.

Thost last two sentences make it sound like the completion ID not
matching the last claim ID is a thing to ignore, but in fact they are
entirely independent statements. This can be confirmed by reading the
source for the Rocket and QEMU PLICs, which have none of the stricter
requirements of the Bluespec PLIC implementation.

This should fix running FreeBSD after r362977, which started to
correctly delay the completion of interrupts until after deferred
handlers had completed (as opposed to after they had been queued).
 2020-12-21 13:32:06 +00:00
Jessica Clarke
6b55d30a8e PLIC: Restore upstream whitespace 2020-12-21 13:32:06 +00:00
Jessica Clarke
e3f94224de Revert "Cause two surprising conditions to not throw slave errors as this is not" 
This reverts commit 4131dcd073.
 2020-12-21 13:03:13 +00:00
Jonathan Woodruff
92ca72a6e2 Fix build error by providing default. 2020-12-18 17:55:18 +00:00
Jonathan Woodruff
84d60d03b1 Merge pull request #6 from nwf/capdirty 
CHERI ISAv8 CapDirty fault priority fix
 2020-12-18 16:48:56 +00:00
jon
f86d4d9dc0 Add counter support to ITLB. 2020-12-17 17:57:43 +00:00
jon
4ddcaff497 Support for data TLB counters. 2020-12-17 16:52:45 +00:00
Jonathan Woodruff
4dd0a73051 Port to internal AXI interfaces for the debug module. 2020-12-17 15:02:05 +00:00
jon
bab989d6d2 Support for stat counters from the tag controller. 
The order of the events is very not tested; 50% chance of being correct.
 2020-12-17 12:38:52 +00:00
jon
4131dcd073 Cause two surprising conditions to not throw slave errors as this is not 
specified and causes kernel panics.  Hopefully the details of what
should happen in these cases is correct, but we shall see...
 2020-12-17 12:37:45 +00:00
jon
fa9931b64c Implement a couple Cache counters in the LLCache. 
These aren't too useful... We don't seem to have normal counters for
loads and stores in the baseline.
 2020-12-15 18:16:21 +00:00
jon
17a7a32092 Use DRegOR instead of immitating latching behaviour. 2020-12-15 16:18:36 +00:00
jon
d64df09d82 Bump to version with DRegOR. 2020-12-15 16:18:18 +00:00
jon
b6a397df52 Support for ICache stat counters. 2020-12-15 14:49:16 +00:00
jon
73d25bf8f5 Support performance counters (hopefully) in the caches. The DCache 
should be fully wired up.
 2020-12-14 18:10:06 +00:00
jon
982758cae7 Bump to version of Bluestuff that has the saturating truncate function. 2020-12-14 12:13:34 +00:00
Jessica Clarke
f6569e2d14 Actually do the intended fix, not just inverting the variable 2020-12-14 10:51:57 +00:00
Jessica Clarke
295b878836 Fix negated CYCLE/INSTRET logic for ASR and make less confusing 2020-12-14 10:50:23 +00:00
jon
6768bf92c7 iMove the store count to the pipeline write. 
It appeared to be counting capabilities in store counter flushes, which,
FI think, is not quite what was intended in this counter.
 2020-12-11 17:16:38 +00:00
jon
19a07882ab CSome style cleanups from chat with Alexandre. 2020-12-11 16:44:59 +00:00
jon
1bae03da9c Implement all the remaining core (not cache) memory stat counters. 2020-12-11 15:48:10 +00:00
jon
d6243be1dd Add a few more core performance counters. 2020-12-04 18:34:56 +00:00
jon
bdc2d494f2 Change name something that makes sense. 2020-12-04 17:12:26 +00:00
jon
3f60c046f7 Fix typo. 2020-12-04 16:51:44 +00:00
jon
f42c3f3577 Merge branch 'cheri-perfmon' into CHERI 2020-12-04 16:29:51 +00:00
jon
5665d2e9cd A more effective Fence count (as some fences go through as the Nop 
iType).
 2020-12-04 16:28:19 +00:00
jon
425c2778c0 Bump Bluestuff to get resetting in the Performance Monitor. 2020-12-03 17:55:03 +00:00
jon
1fb388fb18 Count more things correctly. 2020-12-03 17:54:46 +00:00
jon
8a13b866d7 Bump bluestuff to the one with generalised report width. 2020-12-02 15:31:49 +00:00
jon
4fcc18635a Supporting most architectural counters, wiring them out from 
CommitStage.
Also support multiple events per cycle.
 2020-12-02 15:28:41 +00:00
jon
e99e1e6274 Update CSR names to fullish standard names. 2020-12-02 10:18:25 +00:00
jon
742c4c5c92 Bump Bluestuff. 2020-12-01 18:03:44 +00:00
jon
259d34618c A design that actually passes one performance monitor trace from 
TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.
 2020-12-01 18:02:11 +00:00
Alexandre Joannou
98a9c076cd Update BlueStuff API and Bump BlueStuff and TagController 2020-12-01 14:22:12 +00:00
Jonathan Woodruff
0289bfe17d Fix a couple errors due to changes somehow merged over from the rich_predicted_state branch. 2020-11-09 11:14:11 +00:00
Nathaniel Filardo
6e4c378d4d CHERI ISAv8 CapDirty fault priority fix 
Raise a store page fault if the PTE is missing R or W, even if the store is a
cap store and the PTE is also missing CW, as per the sail spec.

Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
 2020-11-06 19:15:47 +00:00
Jonathan Woodruff
69c697daf7 Changes needed to build for FPGA. 2020-11-06 11:44:33 +00:00
Peter Rugg
bf77ac74ba Fix performance reporting requests for multicore 2020-11-04 12:11:31 +00:00
Peter Rugg
61b88ef987 Generate elf files the correct size 2020-11-02 11:23:07 +00:00
Marno van der Maas
328592b068 Added missing slash in readme 2020-10-29 15:45:17 +00:00
PeterRugg
844bfd5e79 Merge pull request #5 from nwf/capdirty 
Add CHERI PTE CapDirty flag
 2020-10-02 17:17:24 +01:00
Marno van der Maas
ed9541e8d0 Put all dirs for source description in code blocks 2020-10-02 13:09:51 +01:00
Nathaniel Filardo
d4308f0f03 Slightly rework CHERI PTE to add CapDirty flag 
Permissions are consistently checked before dirty flags, now, too.
 2020-09-30 15:40:50 +01:00