Jonathan Woodruff
f255193841
Vastly simplified DMA Connect that does not buffer data at all.
...
This has not been tested yet, but it builds.
2023-02-28 13:28:29 +00:00
Jonathan Woodruff
a38610869d
Merge branch 'jdw57-512axi' of https://github.com/CTSRD-CHERI/Toooba into jdw57-512axi
2023-02-28 13:27:10 +00:00
gameboo
aa68739ab6
Update imports in CoreW
2023-02-23 14:51:24 +00:00
Jonathan Woodruff
a91f15d10c
Merge branch 'CHERI' into jdw57-512axi
2023-02-21 12:18:02 +00:00
Peter Rugg
e981b7625f
Ban illegal JALR and Br encodings
2023-02-16 16:41:39 +00:00
Peter Rugg
8ea0e07ce5
Avoid wedge on repeated debug resumes (with jdw57 and aj443)
...
ConfigReg avoids a compile error
2023-02-10 18:12:08 +00:00
Peter Rugg
50c51e93a1
Add assertion that ndm resets don't get dropped
2023-02-09 14:34:13 +00:00
Peter Rugg
6931201a14
Avoid wedge on repeated debug resumes (with jdw57 and aj443)
...
ConfigReg avoids a compile error
2023-01-31 21:02:17 +00:00
Jonathan Woodruff
06a9221bb1
Changes for GFE hardware build with 512-bit bus.
2022-11-23 13:29:46 +00:00
Jonathan Woodruff
e73d8223ea
Use working tag controller (at 512-bits wide, so quite wasteful for
...
now...).
2022-11-23 10:25:48 +00:00
Jonathan Woodruff
e9d7b85b63
Use working tag controller; merge with more explicit types.
2022-11-23 10:22:04 +00:00
Jonathan Woodruff
5f69c657c1
Use IDs in cache miss transactions to allow reordering.
2022-11-23 10:11:31 +00:00
Alexandre Joannou
98e15acb3d
Bump BlueStuff + use _Periph versions of parameters where needed
2022-11-18 12:07:24 +00:00
Jonathan Woodruff
4af4b647b1
Merge branch 'CHERI' into jdw57-512axi
2022-11-14 14:51:54 +00:00
Jonathan Woodruff
01482abb1b
Move to new name for null tag controller.
2022-11-14 13:48:21 +00:00
Peter Rugg
e120b3427d
Merge branch 'LoadTagsImprove' into CHERI
2022-11-14 13:28:44 +00:00
Jonathan Woodruff
ddf4afaf71
Changes to build with a 512-bit main data bus (with all other busses
...
still 64-bits).
Also, the top-level SoC_Top exposes a 64-bit bus still, so hopefully the
GFE configuration is unchanged.
This passes the isa_tests.
2022-11-11 17:52:32 +00:00
Jonathan Woodruff
066289f8aa
Work in progress.
...
Wd_Data is moved to 512 bits, and LLC_AXI4_Adapter is updated.
Lots of build errors now; a few have been resolved.
2022-11-10 13:51:12 +00:00
Alexandre Joannou
54456b5f50
Fix the non-rvfi_dii build
2022-10-21 09:50:49 +00:00
Franz Fuchs
de0e19ca55
added do not cares for missing struct fields in ROB
2022-10-21 09:22:31 +00:00
Jonathan Woodruff
0562cb18a1
Fix for RVFI_DII build.
2022-10-21 09:18:28 +00:00
Alexandre Joannou
02ba37bf6a
Report the actual running state to the debug module
2022-09-08 13:20:35 +00:00
Alexandre Joannou
a0d471e4f8
Attempt to make toHost setiing behave in src_Testbench
...
Made the proc start method non-blocking on mmio platform and wired in a new way
to set the tohost addr using a control and status request, and bumpped
WindCoreInterface accordingly
2022-09-06 10:42:34 +00:00
Alexandre Joannou
d068df3bd8
uncomment a verbosity check
2022-09-02 12:37:07 +00:00
Alexandre Joannou
2240c87c78
Fix src_Testbench toplevel build for tests and bump BlueStuff
2022-08-25 15:25:55 +00:00
Alexandre Joannou
5bf15adf04
Addressed @francislaus comments
2022-08-17 08:41:27 +00:00
Jonathan Woodruff
1fceb8fa72
Use standard imports as the fixes have been upstreamed.
2022-08-15 16:18:23 +00:00
gameboo
6b51139c9a
Update ack
2022-08-15 16:18:23 +00:00
Alexandre Joannou
947cf8ed7b
NonPipelined API update
2022-08-15 16:18:23 +00:00
Alexandre Joannou
f292c5196d
Rename master_xactor to axiShim in DM_System_Bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
47930189da
Bump BlueStuff + assume external subordinate_0 parameters that match internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
e4bdbfc98a
Bump BlueStuff + add outter subordinate trafic as master to internal bus
2022-08-15 16:18:23 +00:00
Alexandre Joannou
bb62b703c8
Address some rebase nonsense
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a65c93ee98
Update resetting in coreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
2c450aea8c
Some reset adjustments
2022-08-15 16:18:23 +00:00
Alexandre Joannou
a954fd5b38
Use NonPipelined dividers + update "reset_by" in CoreW
2022-08-15 16:18:23 +00:00
Alexandre Joannou
b32da9034b
Fix addr to DM_addr convertion (pointed out by jrtc27)
2022-08-15 16:18:23 +00:00
gameboo
45135a0bee
Don't assume a XILINX tool flow
2022-08-15 16:18:23 +00:00
gameboo
72320b32b2
Update to AXI lite for debug module port
2022-08-15 16:18:23 +00:00
gameboo
b9ee27f390
Update to WindCoreMid + Bump WindCoreInterface
2022-08-15 16:18:23 +00:00
gameboo
812c961360
Introduce the WindCoreInterface
2022-08-15 16:18:23 +00:00
Jonathan Woodruff
8cb96bae5c
Fixes for load address tracing.
2022-08-12 15:09:01 +00:00
Franz Fuchs
2f595167a4
commented out debug print statements in Ras.bsv
2022-07-29 15:41:28 +01:00
Franz Fuchs
e89af4a66d
added typedefs to STLPred
2022-07-26 09:18:20 +01:00
Franz Fuchs
d3e8ef8d90
removed unnecessary declarations in RenameStage
2022-07-25 13:18:50 +01:00
Jonathan Woodruff
a1065616e0
Fix tracing of writes to MMIO addresses.
2022-07-22 15:37:25 +00:00
Franz Fuchs
502e64c24b
fixed not defined warning in ConnectalBramFifo
2022-07-11 15:11:59 +01:00
Franz Fuchs
4abf838d62
implemented missing notFull method in SpecFifo
2022-07-11 14:56:30 +01:00
Franz Fuchs
ad9f2cab3d
used RVFI defines as declared in ToReorderBuffer
2022-07-11 14:18:19 +01:00
Alexandre Joannou
9960d67ed8
Removed some debug print statements
2022-07-11 11:55:40 +00:00
