Peter Rugg
057964e940
Some more tagsparam makefile fixes
2021-03-18 11:09:26 +00:00
Peter Rugg
80fb97cc62
Take Bluestuff-ified Giraffe_IFC from Flute
2021-03-15 12:25:38 +00:00
Peter Rugg
395a9d1c02
Remove unused non-existent libraries from ssith Makefile
2021-03-15 11:26:24 +00:00
Peter Rugg
0e1e2249a6
Default to dual-core builds
2021-03-04 11:54:35 +00:00
Jonathan Woodruff
db08e96596
Add Btb to the component.xml.
2021-03-03 20:27:31 +00:00
Jessica Clarke
9dc27542f3
Use order-only prerequisites for directories
...
Hopefully this stops .depends.mk from being generated more than
necessary, as presumably the fact that compile and simulator both add
new files to build_dir (and Verilog_RTL for Verilator) causes the
timestamp to change and thus make to think .depends.mk is stale.
2021-02-28 04:14:54 +00:00
Peter Rugg
53eb073fb2
Don't track generated Verilog
2021-02-19 19:45:00 +00:00
Peter Rugg
47c94b5a34
Map more RAM in SSITH build
2021-02-19 09:25:41 +00:00
jon
1fbf786294
Add to synthesis file set.
2021-02-17 21:26:54 +00:00
jon
eaf7a4ace7
Add one more missing file and clean up some duplicates.
2021-02-17 18:37:52 +00:00
jon
5ba685b541
Try harder to remove all copies of references to old files.
2021-02-17 16:57:01 +00:00
jon
7a59cad288
Remove more no-longer-generated files from component.xml
2021-02-17 15:54:27 +00:00
jon
059f189bba
Attempt to add all current source files to componenet.xml.
2021-02-17 14:35:49 +00:00
Alexandre Joannou
4c19a34eda
Workaround for scheduling issues when using PERFORMANCE_MONITORING (with jdw57)
2021-02-15 18:07:08 +00:00
Jessica Clarke
fb5339e9ca
Adapt the PLIC instantiation and wiring to support multiple cores
2021-01-31 17:54:43 +00:00
Peter Rugg
f800cdeb77
Prevent spurious warnings
2021-01-30 15:21:38 +00:00
Peter Rugg
e8487e2a1c
Revert "Provide opt-in wedge debugging info"
...
This reverts commit 68d3bd484e
2021-01-19 22:00:16 +00:00
Jessica Clarke
6c98dcb3d8
src_SSITH_P3: Delete stray file references
...
No clue what mkAxiLowPower is. mkPLIC_16_CoreNumX2_7 belongs with the
dual-core fixes, which aren't in the CHERI branch, at least not
currently (and the old mkPLIC_16_2_7 is still referenced in this file
anyway).
2021-01-13 00:59:46 +00:00
Jessica Clarke
1fb31bb255
src_SSITH_P3: Another open-source bsc fix
2021-01-11 21:34:11 +00:00
Jessica Clarke
7ae8689ce5
src_SSITH_P3: Fix build with open-source bsc
...
bsc-contrib puts these under AMBA_TLM3.
2021-01-11 20:57:50 +00:00
Jonathan Woodruff
4dd0a73051
Port to internal AXI interfaces for the debug module.
2020-12-17 15:02:05 +00:00
Jonathan Woodruff
69c697daf7
Changes needed to build for FPGA.
2020-11-06 11:44:33 +00:00
Jessica Clarke
72f49a1109
Regenerate verilog
2020-07-16 19:35:51 +01:00
Jessica Clarke
682ff10d72
Regenerate verilog
2020-07-15 03:16:24 +01:00
Jessica Clarke
e8c1de7793
Regenerate verilog
2020-07-14 19:01:47 +01:00
Jessica Clarke
956c9686a6
src_SSITH_P3: Optimise unspecified values
...
We have a lot of ?s floating around that needlessly constrain logic. As
with Flute, enable optimisations on these in the hope that timing and/or
area improve further.
2020-07-14 17:53:01 +01:00
Jessica Clarke
e89f7a8130
Regenerate verilog
2020-07-13 18:54:53 +01:00
Jessica Clarke
ece8423119
Regenerate verilog
2020-07-11 17:26:00 +01:00
Peter Rugg
6a317d1a00
Prevent instruction fetch to unexpected devices
2020-07-10 17:35:06 +01:00
Jessica Clarke
68d3bd484e
Provide opt-in wedge debugging info
...
When DEBUG_WEDGE is defined, expose the last committed and next in the
reorder buffer PC and corresponding instruction via DMI registers, since
even when the core is wedged and we can't read GPRs etc we can still
interact with the debug module itself. Hopefully this proves useful for
debugging wedges.
2020-07-07 23:59:35 +01:00
Jessica Clarke
40f8109263
Regenerate verilog
2020-07-06 19:32:56 +01:00
Jessica Clarke
9c12b97a09
Regenerate verilog
2020-07-06 01:55:30 +01:00
Jessica Clarke
badf5c8e37
Include xCHERI in ARCH and build directory names
...
Also use RVFI_DII not RVFIDII in the directory names.
This makes everything match Piccolo/Flute rather than having Toooba be a
weird, inconsistent and plain wrong.
2020-07-05 21:41:28 +01:00
Jessica Clarke
0b0b863baa
Replace home-grown dependency script with Bluespec-provided makedepend.tcl
...
This one has the advantage of being able to be called with the same
flags as bsc, rather than needing to pass things through special
environment variables. As a result, revert all our changes to dealing
with BSC_COMPILATION_FLAGS (some of this diff therefore looks strangely
formatted, but it's to match upstream verbatim, and should be left that
way to minimise diffs and avoid conflicts).
2020-07-05 21:26:18 +01:00
Jessica Clarke
cd8e2a15ef
Regenerate verilog
2020-07-02 03:00:55 +01:00
Peter Rugg
dcc506a365
Regenerate verilog
2020-07-01 17:08:08 +01:00
Peter Rugg
f8972768a2
Regenerate verilog
2020-06-30 00:00:29 +01:00
Peter Rugg
258a0921e6
Regenerate verilog
2020-06-25 16:23:40 +01:00
Peter Rugg
a5578a715a
Regenerate verilog
2020-06-24 21:16:57 +01:00
Peter Rugg
7d866f85e7
Regenerate verilog
2020-06-17 13:02:20 +01:00
Peter Rugg
8778369fe5
Merge remote-tracking branch 'upstream/master' into CHERI
2020-06-17 13:01:41 +01:00
Peter Rugg
49a9e5fc64
Remove unconnected signal in simulation
2020-06-17 11:43:28 +01:00
Peter Rugg
4f4bbbbdcb
Add new TagController parameters to synth makefile
2020-06-17 11:40:23 +01:00
Peter Rugg
3117fcc9d5
Regenerate verilog
2020-06-07 16:52:34 +01:00
Peter Rugg
4fbabae1dd
component.xml fixes for synthesis
2020-06-07 16:52:29 +01:00
Peter Rugg
be2c92b291
Regenerate verilog
2020-06-05 17:49:32 +01:00
Peter Rugg
962ade1092
Fixes for synthesis
2020-06-05 17:40:28 +01:00
Peter Rugg
046319b909
Remove Tandem verification
2020-06-03 22:28:31 +01:00
Jonathan Woodruff
3a79b022ea
Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!
2020-03-18 11:35:59 +00:00
rsnikhil
a6a227ed66
Incorporated patches/additions from Joe Stoy after GFE debugging (w. amendment ...)
...
Amendment: RegUNInit.v updated, removing an extraneous RST line.
2020-03-13 16:38:54 -04:00
